src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define THUMB_SUBTRACTION(D, M, N) \
42 int n = N; \
43 int m = M; \
44 D = M - N; \
45 THUMB_SUBTRACTION_S(m, n, D)
46
47#define APPLY(F, ...) F(__VA_ARGS__)
48
49#define COUNT_1(EMITTER, PREFIX, ...) \
50 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
51 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
52
53#define COUNT_2(EMITTER, PREFIX, ...) \
54 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
55 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
56 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
57
58#define COUNT_3(EMITTER, PREFIX, ...) \
59 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
60 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
61 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
62 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
63 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
64
65#define COUNT_4(EMITTER, PREFIX, ...) \
66 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
67 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
68 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
69 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
70 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
71 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
72 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
73 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
74 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
75
76#define COUNT_5(EMITTER, PREFIX, ...) \
77 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
78 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
79 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
80 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
81 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
82 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
83 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
84 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
85 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
86 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
87 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
88 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
89 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
90 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
91 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
92 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
93 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
94
95#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
96 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
97 BODY; \
98 cpu->cycles += 1 + cpu->memory->activePrefetchCycles16; \
99 }
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
102 DEFINE_INSTRUCTION_THUMB(NAME, \
103 int immediate = IMMEDIATE; \
104 int rd = opcode & 0x0007; \
105 int rm = (opcode >> 3) & 0x0007; \
106 BODY;)
107
108#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
109 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
110
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
112 if (!immediate) {
113 cpu->gprs[rd] = cpu->gprs[rm];
114 } else {
115 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate));
116 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
117 }
118 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
119
120DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
121 if (!immediate) {
122 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
123 cpu->gprs[rd] = 0;
124 } else {
125 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1));
126 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
127 }
128 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
129
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
131 if (!immediate) {
132 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
133 if (cpu->cpsr.c) {
134 cpu->gprs[rd] = 0xFFFFFFFF;
135 } else {
136 cpu->gprs[rd] = 0;
137 }
138 } else {
139 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1));
140 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
141 }
142 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
143
144DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
145DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate))
146DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2))
147DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
148DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd]))
149DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
150
151#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
152 DEFINE_INSTRUCTION_THUMB(NAME, \
153 int rm = RM; \
154 int rd = opcode & 0x0007; \
155 int rn = (opcode >> 3) & 0x0007; \
156 BODY;)
157
158#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
159 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
160
161DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
162DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
163
164#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
165 DEFINE_INSTRUCTION_THUMB(NAME, \
166 int immediate = IMMEDIATE; \
167 int rd = opcode & 0x0007; \
168 int rn = (opcode >> 3) & 0x0007; \
169 BODY;)
170
171#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
172 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
173
174DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
175DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
176
177#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
178 DEFINE_INSTRUCTION_THUMB(NAME, \
179 int rd = RD; \
180 int immediate = opcode & 0x00FF; \
181 BODY;)
182
183#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
184 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
185
186DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
187DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
188DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
189DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
190
191#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
192 DEFINE_INSTRUCTION_THUMB(NAME, \
193 int rd = opcode & 0x0007; \
194 int rn = (opcode >> 3) & 0x0007; \
195 BODY;)
196
197DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
198DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
199DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
200DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
201 int rs = cpu->gprs[rn] & 0xFF;
202 if (rs) {
203 if (rs < 32) {
204 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
205 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
206 } else {
207 if (rs > 32) {
208 cpu->cpsr.c = 0;
209 } else {
210 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
211 }
212 cpu->gprs[rd] = 0;
213 }
214 }
215 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
216
217DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
218 int rs = cpu->gprs[rn] & 0xFF;
219 if (rs) {
220 if (rs < 32) {
221 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
222 cpu->gprs[rd] >>= rs;
223 } else {
224 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
225 if (cpu->cpsr.c) {
226 cpu->gprs[rd] = 0xFFFFFFFF;
227 } else {
228 cpu->gprs[rd] = 0;
229 }
230 }
231 }
232 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
233
234DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
235DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
236DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
237DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
238DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
239DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
240DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
241DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
242DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
243DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
244DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
245
246#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
247 DEFINE_INSTRUCTION_THUMB(NAME, \
248 int rd = opcode & 0x0007 | H1; \
249 int rm = (opcode >> 3) & 0x0007 | H2; \
250 BODY;)
251
252#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
253 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
254 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
255 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
256 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
257
258DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
259 cpu->gprs[rd] += cpu->gprs[rm];
260 if (rd == ARM_PC) {
261 THUMB_WRITE_PC;
262 })
263
264DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
265DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
266 cpu->gprs[rd] = cpu->gprs[rm];
267 if (rd == ARM_PC) {
268 THUMB_WRITE_PC;
269 })
270
271#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
272 DEFINE_INSTRUCTION_THUMB(NAME, \
273 int rd = RD; \
274 int immediate = (opcode & 0x00FF) << 2; \
275 BODY;)
276
277#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
278 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
279
280DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
281DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
282DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
283
284DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
285DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
286
287#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
288 DEFINE_INSTRUCTION_THUMB(NAME, \
289 int rm = RM; \
290 int rd = opcode & 0x0007; \
291 int rn = (opcode >> 3) & 0x0007; \
292 BODY;)
293
294#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
295 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
296
297DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
298DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
299DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
300DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
301DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
302DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
303DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
304DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
305
306#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
307 DEFINE_INSTRUCTION_THUMB(NAME, \
308 int rn = (opcode >> 8) & 0x000F; \
309 int rs = RS; \
310 int32_t address = ADDRESS; \
311 int m; \
312 int i; \
313 PRE_BODY; \
314 for LOOP { \
315 if (rs & m) { \
316 BODY; \
317 address OP 4; \
318 } \
319 } \
320 POST_BODY; \
321 WRITEBACK;)
322
323#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
324 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
325
326DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
327 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
328 if (!((1 << rn) & rs)) {
329 cpu->gprs[rn] = address;
330 })
331
332DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
333 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
334 cpu->gprs[rn] = address)
335
336#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
337 DEFINE_INSTRUCTION_THUMB(B ## COND, \
338 if (ARM_COND_ ## COND) { \
339 int8_t immediate = opcode; \
340 cpu->gprs[ARM_PC] += immediate << 1; \
341 THUMB_WRITE_PC; \
342 })
343
344DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
345DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
346DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
347DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
348DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
349DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
350DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
351DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
352DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
353DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
354DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
355DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
356DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
357DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
358
359DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
360DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
361
362DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
363 opcode & 0x00FF,
364 cpu->gprs[ARM_SP],
365 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
366 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
367 +=,
368 , ,
369 cpu->gprs[ARM_SP] = address)
370
371DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
372 opcode & 0x00FF,
373 cpu->gprs[ARM_SP],
374 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
375 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
376 +=,
377 ,
378 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE;
379 address += 4;,
380 cpu->gprs[ARM_SP] = address;
381 THUMB_WRITE_PC;)
382
383DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
384 opcode & 0x00FF,
385 cpu->gprs[ARM_SP] - 4,
386 (m = 0x80, i = 7; m; m >>= 1, --i),
387 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
388 -=,
389 , ,
390 cpu->gprs[ARM_SP] = address + 4)
391
392DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
393 opcode & 0x00FF,
394 cpu->gprs[ARM_SP] - 4,
395 (m = 0x80, i = 7; m; m >>= 1, --i),
396 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
397 -=,
398 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]);
399 address -= 4;,
400 ,
401 cpu->gprs[ARM_SP] = address + 4)
402
403DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
404DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
405DEFINE_INSTRUCTION_THUMB(B,
406 int16_t immediate = (opcode & 0x07FF) << 5;
407 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
408 THUMB_WRITE_PC;)
409
410DEFINE_INSTRUCTION_THUMB(BL1,
411 int16_t immediate = (opcode & 0x07FF) << 5;
412 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
413
414DEFINE_INSTRUCTION_THUMB(BL2,
415 uint16_t immediate = (opcode & 0x07FF) << 1;
416 uint32_t pc = cpu->gprs[ARM_PC];
417 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
418 cpu->gprs[ARM_LR] = pc - 1;
419 THUMB_WRITE_PC;)
420
421DEFINE_INSTRUCTION_THUMB(BX,
422 int rm = (opcode >> 3) & 0xF;
423 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
424 int misalign = 0;
425 if (rm == ARM_PC) {
426 misalign = cpu->gprs[rm] & 0x00000002;
427 }
428 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign;
429 if (cpu->executionMode == MODE_THUMB) {
430 THUMB_WRITE_PC;
431 } else {
432 ARM_WRITE_PC;
433 })
434
435DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
436
437#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
438 EMITTER ## NAME
439
440#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
441 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
442 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
443 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
444 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
445
446#define DUMMY(X, ...) X,
447#define DUMMY_4(...) \
448 DUMMY(__VA_ARGS__) \
449 DUMMY(__VA_ARGS__) \
450 DUMMY(__VA_ARGS__) \
451 DUMMY(__VA_ARGS__)
452
453#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
454 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
455 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
456 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
457 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
458 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
459 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
460 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
461 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
462 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
463 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
464 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
465 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
466 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
467 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
468 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
469 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
470 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
471 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
472 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
473 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
474 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
475 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
476 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
477 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
478 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
479 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
480 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
481 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
482 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
483 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
484 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
485 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
486 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
487 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
488 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
489 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
490 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
491 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
492 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
493 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
494 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
495 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
496 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
497 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
498 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
499 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
500 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
501 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
502 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
503 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
504 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
505 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
506 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
507 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
508 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
509 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
510 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
511 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
512 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
513 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
514 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
515 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
516 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
517 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
518 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
519 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
520 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
521 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
522 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
523 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
524 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
525 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
526 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
527 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
528 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
529 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
530 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
531 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
532 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
533 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
534 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
535 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
536 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
537 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
538 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
539 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
540 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
541 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
542 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
543 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
544 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
545
546static const ThumbInstruction _thumbTable[0x400] = {
547 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
548};