1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include "util/common.h"
 10
 11enum {
 12	ARM_SP = 13,
 13	ARM_LR = 14,
 14	ARM_PC = 15
 15};
 16
 17enum ExecutionMode {
 18	MODE_ARM = 0,
 19	MODE_THUMB = 1
 20};
 21
 22enum PrivilegeMode {
 23	MODE_USER = 0x10,
 24	MODE_FIQ = 0x11,
 25	MODE_IRQ = 0x12,
 26	MODE_SUPERVISOR = 0x13,
 27	MODE_ABORT = 0x17,
 28	MODE_UNDEFINED = 0x1B,
 29	MODE_SYSTEM = 0x1F
 30};
 31
 32enum WordSize {
 33	WORD_SIZE_ARM = 4,
 34	WORD_SIZE_THUMB = 2
 35};
 36
 37enum ExecutionVector {
 38	BASE_RESET = 0x00000000,
 39	BASE_UNDEF = 0x00000004,
 40	BASE_SWI = 0x00000008,
 41	BASE_PABT = 0x0000000C,
 42	BASE_DABT = 0x00000010,
 43	BASE_IRQ = 0x00000018,
 44	BASE_FIQ = 0x0000001C
 45};
 46
 47enum RegisterBank {
 48	BANK_NONE = 0,
 49	BANK_FIQ = 1,
 50	BANK_IRQ = 2,
 51	BANK_SUPERVISOR = 3,
 52	BANK_ABORT = 4,
 53	BANK_UNDEFINED = 5
 54};
 55
 56enum LSMDirection {
 57	LSM_B = 1,
 58	LSM_D = 2,
 59	LSM_IA = 0,
 60	LSM_IB = 1,
 61	LSM_DA = 2,
 62	LSM_DB = 3
 63};
 64
 65struct ARMCore;
 66
 67union PSR {
 68	struct {
 69#if defined(__POWERPC__) || defined(__PPC__)
 70		unsigned n : 1;
 71		unsigned z : 1;
 72		unsigned c : 1;
 73		unsigned v : 1;
 74		unsigned : 20;
 75		unsigned i : 1;
 76		unsigned f : 1;
 77		enum ExecutionMode t : 1;
 78		enum PrivilegeMode priv : 5;
 79#else
 80		enum PrivilegeMode priv : 5;
 81		enum ExecutionMode t : 1;
 82		unsigned f : 1;
 83		unsigned i : 1;
 84		unsigned : 20;
 85		unsigned v : 1;
 86		unsigned c : 1;
 87		unsigned z : 1;
 88		unsigned n : 1;
 89#endif
 90	};
 91
 92	int32_t packed;
 93};
 94
 95struct ARMMemory {
 96	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 97	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 98	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 99
100	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
101	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
102	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
103
104	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
105	                         int* cycleCounter);
106	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
107	                          int* cycleCounter);
108
109	uint32_t* activeRegion;
110	uint32_t activeMask;
111	uint32_t activeSeqCycles32;
112	uint32_t activeSeqCycles16;
113	uint32_t activeNonseqCycles32;
114	uint32_t activeNonseqCycles16;
115	int32_t (*stall)(struct ARMCore*, int32_t wait);
116	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
117};
118
119struct ARMInterruptHandler {
120	void (*reset)(struct ARMCore* cpu);
121	void (*processEvents)(struct ARMCore* cpu);
122	void (*swi16)(struct ARMCore* cpu, int immediate);
123	void (*swi32)(struct ARMCore* cpu, int immediate);
124	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
125	void (*bkpt16)(struct ARMCore* cpu, int immediate);
126	void (*bkpt32)(struct ARMCore* cpu, int immediate);
127	void (*readCPSR)(struct ARMCore* cpu);
128
129	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
130};
131
132struct ARMComponent {
133	uint32_t id;
134	void (*init)(struct ARMCore* cpu, struct ARMComponent* component);
135	void (*deinit)(struct ARMComponent* component);
136};
137
138struct ARMCore {
139	int32_t gprs[16];
140	union PSR cpsr;
141	union PSR spsr;
142
143	int32_t cycles;
144	int32_t nextEvent;
145	int halted;
146
147	int32_t bankedRegisters[6][7];
148	int32_t bankedSPSRs[6];
149
150	int32_t shifterOperand;
151	int32_t shifterCarryOut;
152
153	uint32_t prefetch[2];
154	enum ExecutionMode executionMode;
155	enum PrivilegeMode privilegeMode;
156
157	struct ARMMemory memory;
158	struct ARMInterruptHandler irqh;
159
160	struct ARMComponent* master;
161
162	size_t numComponents;
163	struct ARMComponent** components;
164};
165
166void ARMInit(struct ARMCore* cpu);
167void ARMDeinit(struct ARMCore* cpu);
168void ARMSetComponents(struct ARMCore* cpu, struct ARMComponent* master, int extra, struct ARMComponent** extras);
169void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
170void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
171
172void ARMReset(struct ARMCore* cpu);
173void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
174void ARMRaiseIRQ(struct ARMCore*);
175void ARMRaiseSWI(struct ARMCore*);
176void ARMRaiseUndefined(struct ARMCore*);
177
178void ARMRun(struct ARMCore* cpu);
179void ARMRunLoop(struct ARMCore* cpu);
180void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
181
182#endif