src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "io.h"
7
8#include "gb/gb.h"
9#include "gb/sio.h"
10#include "gb/serialize.h"
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_UNK75] = 0x8F,
105 [REG_IE] = 0xE0,
106};
107
108void GBIOInit(struct GB* gb) {
109 memset(gb->memory.io, 0, sizeof(gb->memory.io));
110}
111
112void GBIOReset(struct GB* gb) {
113 memset(gb->memory.io, 0, sizeof(gb->memory.io));
114
115 GBIOWrite(gb, REG_TIMA, 0);
116 GBIOWrite(gb, REG_TMA, 0);
117 GBIOWrite(gb, REG_TAC, 0);
118 GBIOWrite(gb, REG_IF, 1);
119 GBIOWrite(gb, REG_NR52, 0xF1);
120 GBIOWrite(gb, REG_NR10, 0x80);
121 GBIOWrite(gb, REG_NR11, 0xBF);
122 GBIOWrite(gb, REG_NR12, 0xF3);
123 GBIOWrite(gb, REG_NR13, 0xF3);
124 GBIOWrite(gb, REG_NR14, 0xBF);
125 GBIOWrite(gb, REG_NR21, 0x3F);
126 GBIOWrite(gb, REG_NR22, 0x00);
127 GBIOWrite(gb, REG_NR24, 0xBF);
128 GBIOWrite(gb, REG_NR30, 0x7F);
129 GBIOWrite(gb, REG_NR31, 0xFF);
130 GBIOWrite(gb, REG_NR32, 0x9F);
131 GBIOWrite(gb, REG_NR34, 0xBF);
132 GBIOWrite(gb, REG_NR41, 0xFF);
133 GBIOWrite(gb, REG_NR42, 0x00);
134 GBIOWrite(gb, REG_NR43, 0x00);
135 GBIOWrite(gb, REG_NR44, 0xBF);
136 GBIOWrite(gb, REG_NR50, 0x77);
137 GBIOWrite(gb, REG_NR51, 0xF3);
138 GBIOWrite(gb, REG_LCDC, 0x91);
139 GBIOWrite(gb, REG_SCY, 0x00);
140 GBIOWrite(gb, REG_SCX, 0x00);
141 GBIOWrite(gb, REG_LYC, 0x00);
142 GBIOWrite(gb, REG_BGP, 0xFC);
143 GBIOWrite(gb, REG_OBP0, 0xFF);
144 GBIOWrite(gb, REG_OBP1, 0xFF);
145 GBIOWrite(gb, REG_WY, 0x00);
146 GBIOWrite(gb, REG_WX, 0x00);
147 GBIOWrite(gb, REG_VBK, 0);
148 GBIOWrite(gb, REG_BCPS, 0);
149 GBIOWrite(gb, REG_OCPS, 0);
150 GBIOWrite(gb, REG_SVBK, 1);
151 GBIOWrite(gb, REG_HDMA1, 0xFF);
152 GBIOWrite(gb, REG_HDMA2, 0xFF);
153 GBIOWrite(gb, REG_HDMA3, 0xFF);
154 GBIOWrite(gb, REG_HDMA4, 0xFF);
155 gb->memory.io[REG_HDMA5] = 0xFF;
156 GBIOWrite(gb, REG_IE, 0x00);
157}
158
159void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
160 switch (address) {
161 case REG_SC:
162 GBSIOWriteSC(&gb->sio, value);
163 break;
164 case REG_DIV:
165 GBTimerDivReset(&gb->timer);
166 return;
167 case REG_NR10:
168 if (gb->audio.enable) {
169 GBAudioWriteNR10(&gb->audio, value);
170 } else {
171 value = 0;
172 }
173 break;
174 case REG_NR11:
175 if (gb->audio.enable) {
176 GBAudioWriteNR11(&gb->audio, value);
177 } else {
178 if (gb->audio.style == GB_AUDIO_DMG) {
179 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
180 }
181 value = 0;
182 }
183 break;
184 case REG_NR12:
185 if (gb->audio.enable) {
186 GBAudioWriteNR12(&gb->audio, value);
187 } else {
188 value = 0;
189 }
190 break;
191 case REG_NR13:
192 if (gb->audio.enable) {
193 GBAudioWriteNR13(&gb->audio, value);
194 } else {
195 value = 0;
196 }
197 break;
198 case REG_NR14:
199 if (gb->audio.enable) {
200 GBAudioWriteNR14(&gb->audio, value);
201 } else {
202 value = 0;
203 }
204 break;
205 case REG_NR21:
206 if (gb->audio.enable) {
207 GBAudioWriteNR21(&gb->audio, value);
208 } else {
209 if (gb->audio.style == GB_AUDIO_DMG) {
210 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
211 }
212 value = 0;
213 }
214 break;
215 case REG_NR22:
216 if (gb->audio.enable) {
217 GBAudioWriteNR22(&gb->audio, value);
218 } else {
219 value = 0;
220 }
221 break;
222 case REG_NR23:
223 if (gb->audio.enable) {
224 GBAudioWriteNR23(&gb->audio, value);
225 } else {
226 value = 0;
227 }
228 break;
229 case REG_NR24:
230 if (gb->audio.enable) {
231 GBAudioWriteNR24(&gb->audio, value);
232 } else {
233 value = 0;
234 }
235 break;
236 case REG_NR30:
237 if (gb->audio.enable) {
238 GBAudioWriteNR30(&gb->audio, value);
239 } else {
240 value = 0;
241 }
242 break;
243 case REG_NR31:
244 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
245 GBAudioWriteNR31(&gb->audio, value);
246 } else {
247 value = 0;
248 }
249 break;
250 case REG_NR32:
251 if (gb->audio.enable) {
252 GBAudioWriteNR32(&gb->audio, value);
253 } else {
254 value = 0;
255 }
256 break;
257 case REG_NR33:
258 if (gb->audio.enable) {
259 GBAudioWriteNR33(&gb->audio, value);
260 } else {
261 value = 0;
262 }
263 break;
264 case REG_NR34:
265 if (gb->audio.enable) {
266 GBAudioWriteNR34(&gb->audio, value);
267 } else {
268 value = 0;
269 }
270 break;
271 case REG_NR41:
272 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
273 GBAudioWriteNR41(&gb->audio, value);
274 } else {
275 value = 0;
276 }
277 break;
278 case REG_NR42:
279 if (gb->audio.enable) {
280 GBAudioWriteNR42(&gb->audio, value);
281 } else {
282 value = 0;
283 }
284 break;
285 case REG_NR43:
286 if (gb->audio.enable) {
287 GBAudioWriteNR43(&gb->audio, value);
288 } else {
289 value = 0;
290 }
291 break;
292 case REG_NR44:
293 if (gb->audio.enable) {
294 GBAudioWriteNR44(&gb->audio, value);
295 } else {
296 value = 0;
297 }
298 break;
299 case REG_NR50:
300 if (gb->audio.enable) {
301 GBAudioWriteNR50(&gb->audio, value);
302 } else {
303 value = 0;
304 }
305 break;
306 case REG_NR51:
307 if (gb->audio.enable) {
308 GBAudioWriteNR51(&gb->audio, value);
309 } else {
310 value = 0;
311 }
312 break;
313 case REG_NR52:
314 GBAudioWriteNR52(&gb->audio, value);
315 value &= 0x80;
316 value |= gb->memory.io[REG_NR52] & 0x0F;
317 break;
318 case REG_WAVE_0:
319 case REG_WAVE_1:
320 case REG_WAVE_2:
321 case REG_WAVE_3:
322 case REG_WAVE_4:
323 case REG_WAVE_5:
324 case REG_WAVE_6:
325 case REG_WAVE_7:
326 case REG_WAVE_8:
327 case REG_WAVE_9:
328 case REG_WAVE_A:
329 case REG_WAVE_B:
330 case REG_WAVE_C:
331 case REG_WAVE_D:
332 case REG_WAVE_E:
333 case REG_WAVE_F:
334 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
335 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
336 } else if(gb->audio.ch3.readable) {
337 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
338 }
339 break;
340 case REG_JOYP:
341 case REG_SB:
342 case REG_TIMA:
343 case REG_TMA:
344 case REG_LYC:
345 // Handled transparently by the registers
346 break;
347 case REG_TAC:
348 value = GBTimerUpdateTAC(&gb->timer, value);
349 break;
350 case REG_IF:
351 gb->memory.io[REG_IF] = value | 0xE0;
352 GBUpdateIRQs(gb);
353 return;
354 case REG_LCDC:
355 // TODO: handle GBC differences
356 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
357 GBVideoWriteLCDC(&gb->video, value);
358 break;
359 case REG_DMA:
360 GBMemoryDMA(gb, value << 8);
361 break;
362 case REG_SCY:
363 case REG_SCX:
364 case REG_WY:
365 case REG_WX:
366 GBVideoProcessDots(&gb->video);
367 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
368 break;
369 case REG_BGP:
370 case REG_OBP0:
371 case REG_OBP1:
372 GBVideoProcessDots(&gb->video);
373 GBVideoWritePalette(&gb->video, address, value);
374 break;
375 case REG_STAT:
376 GBVideoWriteSTAT(&gb->video, value);
377 value = gb->video.stat;
378 break;
379 case 0x50:
380 if (gb->memory.romBase != gb->memory.rom) {
381 free(gb->memory.romBase);
382 gb->memory.romBase = gb->memory.rom;
383 }
384 break;
385 case REG_IE:
386 gb->memory.ie = value;
387 GBUpdateIRQs(gb);
388 return;
389 default:
390 if (gb->model >= GB_MODEL_CGB) {
391 switch (address) {
392 case REG_KEY1:
393 value &= 0x1;
394 value |= gb->memory.io[address] & 0x80;
395 break;
396 case REG_VBK:
397 GBVideoSwitchBank(&gb->video, value);
398 break;
399 case REG_HDMA1:
400 case REG_HDMA2:
401 case REG_HDMA3:
402 case REG_HDMA4:
403 // Handled transparently by the registers
404 break;
405 case REG_HDMA5:
406 GBMemoryWriteHDMA5(gb, value);
407 value &= 0x7F;
408 break;
409 case REG_BCPS:
410 gb->video.bcpIndex = value & 0x3F;
411 gb->video.bcpIncrement = value & 0x80;
412 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
413 break;
414 case REG_BCPD:
415 GBVideoProcessDots(&gb->video);
416 GBVideoWritePalette(&gb->video, address, value);
417 return;
418 case REG_OCPS:
419 gb->video.ocpIndex = value & 0x3F;
420 gb->video.ocpIncrement = value & 0x80;
421 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
422 break;
423 case REG_OCPD:
424 GBVideoProcessDots(&gb->video);
425 GBVideoWritePalette(&gb->video, address, value);
426 return;
427 case REG_SVBK:
428 GBMemorySwitchWramBank(&gb->memory, value);
429 value = gb->memory.wramCurrentBank;
430 break;
431 default:
432 goto failed;
433 }
434 goto success;
435 }
436 failed:
437 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
438 if (address >= GB_SIZE_IO) {
439 return;
440 }
441 break;
442 }
443 success:
444 gb->memory.io[address] = value;
445}
446
447static uint8_t _readKeys(struct GB* gb) {
448 uint8_t keys = *gb->keySource;
449 switch (gb->memory.io[REG_JOYP] & 0x30) {
450 case 0x30:
451 keys = 0;
452 break;
453 case 0x20:
454 keys >>= 4;
455 break;
456 case 0x10:
457 break;
458 case 0x00:
459 keys |= keys >> 4;
460 break;
461 }
462 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
463}
464
465uint8_t GBIORead(struct GB* gb, unsigned address) {
466 switch (address) {
467 case REG_JOYP:
468 return _readKeys(gb);
469 case REG_IE:
470 return gb->memory.ie;
471 case REG_WAVE_0:
472 case REG_WAVE_1:
473 case REG_WAVE_2:
474 case REG_WAVE_3:
475 case REG_WAVE_4:
476 case REG_WAVE_5:
477 case REG_WAVE_6:
478 case REG_WAVE_7:
479 case REG_WAVE_8:
480 case REG_WAVE_9:
481 case REG_WAVE_A:
482 case REG_WAVE_B:
483 case REG_WAVE_C:
484 case REG_WAVE_D:
485 case REG_WAVE_E:
486 case REG_WAVE_F:
487 if (gb->audio.playingCh3) {
488 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
489 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
490 } else {
491 return 0xFF;
492 }
493 } else {
494 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
495 }
496 break;
497 case REG_SB:
498 case REG_SC:
499 case REG_IF:
500 case REG_NR10:
501 case REG_NR11:
502 case REG_NR12:
503 case REG_NR14:
504 case REG_NR21:
505 case REG_NR22:
506 case REG_NR24:
507 case REG_NR30:
508 case REG_NR32:
509 case REG_NR34:
510 case REG_NR41:
511 case REG_NR42:
512 case REG_NR43:
513 case REG_NR44:
514 case REG_NR50:
515 case REG_NR51:
516 case REG_NR52:
517 case REG_DIV:
518 case REG_TIMA:
519 case REG_TMA:
520 case REG_TAC:
521 case REG_STAT:
522 case REG_LCDC:
523 case REG_SCY:
524 case REG_SCX:
525 case REG_LY:
526 case REG_LYC:
527 case REG_BGP:
528 case REG_OBP0:
529 case REG_OBP1:
530 case REG_WY:
531 case REG_WX:
532 // Handled transparently by the registers
533 break;
534 default:
535 if (gb->model >= GB_MODEL_CGB) {
536 switch (address) {
537 case REG_KEY1:
538 case REG_VBK:
539 case REG_HDMA1:
540 case REG_HDMA2:
541 case REG_HDMA3:
542 case REG_HDMA4:
543 case REG_HDMA5:
544 case REG_BCPS:
545 case REG_BCPD:
546 case REG_OCPS:
547 case REG_OCPD:
548 case REG_SVBK:
549 // Handled transparently by the registers
550 goto success;
551 default:
552 break;
553 }
554 }
555 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
556 return 0xFF;
557 }
558 success:
559 return gb->memory.io[address] | _registerMask[address];
560}
561
562struct GBSerializedState;
563void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
564 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
565 state->ie = gb->memory.ie;
566}
567
568void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
569 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
570 gb->memory.ie = state->ie;
571 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
572 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
573 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
574 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
575 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
576}