src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-arm.h"
7
8#include "arm.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
188
189#define ARM_ADDITION_S(M, N, D) \
190 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
191 cpu->cpsr = cpu->spsr; \
192 _ARMReadCPSR(cpu); \
193 } else { \
194 cpu->cpsr.n = ARM_SIGN(D); \
195 cpu->cpsr.z = !(D); \
196 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
197 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
198 }
199
200#define ARM_SUBTRACTION_S(M, N, D) \
201 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
202 cpu->cpsr = cpu->spsr; \
203 _ARMReadCPSR(cpu); \
204 } else { \
205 cpu->cpsr.n = ARM_SIGN(D); \
206 cpu->cpsr.z = !(D); \
207 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
208 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
209 }
210
211#define ARM_NEUTRAL_S(M, N, D) \
212 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
213 cpu->cpsr = cpu->spsr; \
214 _ARMReadCPSR(cpu); \
215 } else { \
216 cpu->cpsr.n = ARM_SIGN(D); \
217 cpu->cpsr.z = !(D); \
218 cpu->cpsr.c = cpu->shifterCarryOut; \
219 }
220
221#define ARM_NEUTRAL_HI_S(DLO, DHI) \
222 cpu->cpsr.n = ARM_SIGN(DHI); \
223 cpu->cpsr.z = !((DHI) | (DLO));
224
225#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
226#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
227#define ADDR_MODE_2_ADDRESS (address)
228#define ADDR_MODE_2_RN (cpu->gprs[rn])
229#define ADDR_MODE_2_RM (cpu->gprs[rm])
230#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
231#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
232#define ADDR_MODE_2_WRITEBACK(ADDR) \
233 cpu->gprs[rn] = ADDR; \
234 if (UNLIKELY(rn == ARM_PC)) { \
235 ARM_WRITE_PC; \
236 }
237
238#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
239#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
240#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
241#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
242
243#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
244#define ADDR_MODE_3_RN ADDR_MODE_2_RN
245#define ADDR_MODE_3_RM ADDR_MODE_2_RM
246#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
247#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
248#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
249
250#define ADDR_MODE_4_WRITEBACK_LDM \
251 if (!((1 << rn) & rs)) { \
252 cpu->gprs[rn] = address; \
253 }
254
255#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
256
257#define ARM_LOAD_POST_BODY \
258 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
259 if (rd == ARM_PC) { \
260 ARM_WRITE_PC; \
261 }
262
263#define ARM_STORE_POST_BODY \
264 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
265
266#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
267 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
268 int currentCycles = ARM_PREFETCH_CYCLES; \
269 BODY; \
270 cpu->cycles += currentCycles; \
271 }
272
273#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
274 DEFINE_INSTRUCTION_ARM(NAME, \
275 int rd = (opcode >> 12) & 0xF; \
276 int rn = (opcode >> 16) & 0xF; \
277 UNUSED(rn); \
278 SHIFTER(cpu, opcode); \
279 BODY; \
280 S_BODY; \
281 if (rd == ARM_PC) { \
282 if (cpu->executionMode == MODE_ARM) { \
283 ARM_WRITE_PC; \
284 } else { \
285 THUMB_WRITE_PC; \
286 } \
287 })
288
289#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
300
301#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
307
308#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
309 DEFINE_INSTRUCTION_ARM(NAME, \
310 int rd = (opcode >> 12) & 0xF; \
311 int rdHi = (opcode >> 16) & 0xF; \
312 int rs = (opcode >> 8) & 0xF; \
313 int rm = opcode & 0xF; \
314 if (rdHi == ARM_PC || rd == ARM_PC) { \
315 return; \
316 } \
317 ARM_WAIT_MUL(cpu->gprs[rs]); \
318 BODY; \
319 S_BODY; \
320 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
321
322#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
323 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
324 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
325
326#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
327 DEFINE_INSTRUCTION_ARM(NAME, \
328 uint32_t address; \
329 int rn = (opcode >> 16) & 0xF; \
330 int rd = (opcode >> 12) & 0xF; \
331 int rm = opcode & 0xF; \
332 UNUSED(rm); \
333 address = ADDRESS; \
334 WRITEBACK; \
335 BODY;)
336
337#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
338 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
344
345#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
346 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
356
357#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
370
371#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
374
375#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
376 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
377 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
378 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
379 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
382
383#define ARM_MS_PRE \
384 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
385 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
386
387#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
388
389#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
390 DEFINE_INSTRUCTION_ARM(NAME, \
391 int rn = (opcode >> 16) & 0xF; \
392 int rs = opcode & 0x0000FFFF; \
393 uint32_t address = cpu->gprs[rn]; \
394 S_PRE; \
395 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
396 S_POST; \
397 POST_BODY; \
398 WRITEBACK;)
399
400
401#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
402 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
403 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
404 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
405 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
406 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
407 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
408 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
409 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
410 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
411 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
412 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
418
419// Begin ALU definitions
420
421DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
422 int32_t n = cpu->gprs[rn];
423 cpu->gprs[rd] = n + cpu->shifterOperand;)
424
425DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
426 int32_t n = cpu->gprs[rn];
427 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
428
429DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
430 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
431
432DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
433 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
434
435DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
436 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
437
438DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
439 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
440
441DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
442 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
443
444DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
445 cpu->gprs[rd] = cpu->shifterOperand;)
446
447DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
448 cpu->gprs[rd] = ~cpu->shifterOperand;)
449
450DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
451 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
452
453DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
454 int32_t n = cpu->gprs[rn];
455 cpu->gprs[rd] = cpu->shifterOperand - n;)
456
457DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
458 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
459 cpu->gprs[rd] = cpu->shifterOperand - n;)
460
461DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
462 int32_t n = cpu->gprs[rn];
463 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
464 cpu->gprs[rd] = n - shifterOperand;)
465
466DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
467 int32_t n = cpu->gprs[rn];
468 cpu->gprs[rd] = n - cpu->shifterOperand;)
469
470DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
471 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
472
473DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
474 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
475
476// End ALU definitions
477
478// Begin multiply definitions
479
480DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
481DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
482
483DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
484 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
485 int32_t dm = cpu->gprs[rd];
486 int32_t dn = d;
487 cpu->gprs[rd] = dm + dn;
488 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
489 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
490
491DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
492 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
493 cpu->gprs[rd] = d;
494 cpu->gprs[rdHi] = d >> 32;,
495 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
496
497DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
498 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
499 int32_t dm = cpu->gprs[rd];
500 int32_t dn = d;
501 cpu->gprs[rd] = dm + dn;
502 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
503 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
504
505DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
506 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
507 cpu->gprs[rd] = d;
508 cpu->gprs[rdHi] = d >> 32;,
509 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
510
511// End multiply definitions
512
513// Begin load/store definitions
514
515DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
516DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
517DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
518DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
519DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
520DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
521DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
522DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
523
524DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
525 enum PrivilegeMode priv = cpu->privilegeMode;
526 ARMSetPrivilegeMode(cpu, MODE_USER);
527 cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles);
528 ARMSetPrivilegeMode(cpu, priv);
529 ARM_LOAD_POST_BODY;)
530
531DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
532 enum PrivilegeMode priv = cpu->privilegeMode;
533 ARMSetPrivilegeMode(cpu, MODE_USER);
534 cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles);
535 ARMSetPrivilegeMode(cpu, priv);
536 ARM_LOAD_POST_BODY;)
537
538DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
539 enum PrivilegeMode priv = cpu->privilegeMode;
540 ARMSetPrivilegeMode(cpu, MODE_USER);
541 cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles);
542 ARMSetPrivilegeMode(cpu, priv);
543 ARM_STORE_POST_BODY;)
544
545DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
546 enum PrivilegeMode priv = cpu->privilegeMode;
547 ARMSetPrivilegeMode(cpu, MODE_USER);
548 cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles);
549 ARMSetPrivilegeMode(cpu, priv);
550 ARM_STORE_POST_BODY;)
551
552DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
553 load,
554 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
555 if (rs & 0x8000) {
556 ARM_WRITE_PC;
557 })
558
559DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
560 store,
561 ARM_STORE_POST_BODY;)
562
563DEFINE_INSTRUCTION_ARM(SWP,
564 int rm = opcode & 0xF;
565 int rd = (opcode >> 12) & 0xF;
566 int rn = (opcode >> 16) & 0xF;
567 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
568 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
569 cpu->gprs[rd] = d;)
570
571DEFINE_INSTRUCTION_ARM(SWPB,
572 int rm = opcode & 0xF;
573 int rd = (opcode >> 12) & 0xF;
574 int rn = (opcode >> 16) & 0xF;
575 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
576 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
577 cpu->gprs[rd] = d;)
578
579// End load/store definitions
580
581// Begin branch definitions
582
583DEFINE_INSTRUCTION_ARM(B,
584 int32_t offset = opcode << 8;
585 offset >>= 6;
586 cpu->gprs[ARM_PC] += offset;
587 ARM_WRITE_PC;)
588
589DEFINE_INSTRUCTION_ARM(BL,
590 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
591 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
592 cpu->gprs[ARM_PC] += immediate >> 6;
593 ARM_WRITE_PC;)
594
595DEFINE_INSTRUCTION_ARM(BX,
596 int rm = opcode & 0x0000000F;
597 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
598 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
599 if (cpu->executionMode == MODE_THUMB) {
600 THUMB_WRITE_PC;
601 } else {
602 ARM_WRITE_PC;
603 })
604
605// End branch definitions
606
607// Begin coprocessor definitions
608
609DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
610DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
611DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
612DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
613DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
614
615// Begin miscellaneous definitions
616
617DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
618DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
619
620DEFINE_INSTRUCTION_ARM(MSR,
621 int c = opcode & 0x00010000;
622 int f = opcode & 0x00080000;
623 int32_t operand = cpu->gprs[opcode & 0x0000000F];
624 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
625 if (mask & PSR_USER_MASK) {
626 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
627 }
628 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
629 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
630 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
631 }
632 _ARMReadCPSR(cpu);)
633
634DEFINE_INSTRUCTION_ARM(MSRR,
635 int c = opcode & 0x00010000;
636 int f = opcode & 0x00080000;
637 int32_t operand = cpu->gprs[opcode & 0x0000000F];
638 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
639 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
640 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
641
642DEFINE_INSTRUCTION_ARM(MRS, \
643 int rd = (opcode >> 12) & 0xF; \
644 cpu->gprs[rd] = cpu->cpsr.packed;)
645
646DEFINE_INSTRUCTION_ARM(MRSR, \
647 int rd = (opcode >> 12) & 0xF; \
648 cpu->gprs[rd] = cpu->spsr.packed;)
649
650DEFINE_INSTRUCTION_ARM(MSRI,
651 int c = opcode & 0x00010000;
652 int f = opcode & 0x00080000;
653 int rotate = (opcode & 0x00000F00) >> 7;
654 int32_t operand = ROR(opcode & 0x000000FF, rotate);
655 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
656 if (mask & PSR_USER_MASK) {
657 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
658 }
659 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
660 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
661 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
662 }
663 _ARMReadCPSR(cpu);)
664
665DEFINE_INSTRUCTION_ARM(MSRRI,
666 int c = opcode & 0x00010000;
667 int f = opcode & 0x00080000;
668 int rotate = (opcode & 0x00000F00) >> 7;
669 int32_t operand = ROR(opcode & 0x000000FF, rotate);
670 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
671 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
672 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
673
674DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
675
676const ARMInstruction _armTable[0x1000] = {
677 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
678};