src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
16static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
17static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
18static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
19static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
20static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
21
22void GBAMemoryInit(struct GBAMemory* memory) {
23 memory->d.load32 = GBALoad32;
24 memory->d.load16 = GBALoad16;
25 memory->d.loadU16 = GBALoadU16;
26 memory->d.load8 = GBALoad8;
27 memory->d.loadU8 = GBALoadU8;
28 memory->d.store32 = GBAStore32;
29 memory->d.store16 = GBAStore16;
30 memory->d.store8 = GBAStore8;
31
32 memory->bios = (uint32_t*) hleBios;
33 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
34 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->rom = 0;
36 memset(memory->io, 0, sizeof(memory->io));
37 memset(memory->dma, 0, sizeof(memory->dma));
38
39 if (!memory->wram || !memory->iwram) {
40 GBAMemoryDeinit(memory);
41 memory->p->errno = GBA_OUT_OF_MEMORY;
42 memory->p->errstr = GBA_CANNOT_MMAP;
43 }
44
45 GBASavedataInit(&memory->savedata, "test.sav");
46
47 int i;
48 for (i = 0; i < 16; ++i) {
49 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
50 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
51 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
53 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
54 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 }
56 for (; i < 256; ++i) {
57 memory->waitstates16[i] = 0;
58 memory->waitstatesSeq16[i] = 0;
59 memory->waitstatesPrefetch16[i] = 0;
60 memory->waitstates32[i] = 0;
61 memory->waitstatesSeq32[i] = 0;
62 memory->waitstatesPrefetch32[i] = 0;
63 }
64
65 memory->activeRegion = 0;
66 memory->d.activeRegion = 0;
67 memory->d.activeMask = 0;
68 memory->d.setActiveRegion = GBASetActiveRegion;
69 memory->d.activePrefetchCycles32 = 0;
70 memory->d.activePrefetchCycles16 = 0;
71}
72
73void GBAMemoryDeinit(struct GBAMemory* memory) {
74 munmap(memory->wram, SIZE_WORKING_RAM);
75 munmap(memory->iwram, SIZE_WORKING_IRAM);
76 GBASavedataDeinit(&memory->savedata);
77}
78
79static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
80 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
81
82 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[address >> BASE_OFFSET];
83 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[address >> BASE_OFFSET];
84 gbaMemory->activeRegion = address >> BASE_OFFSET;
85 switch (address & ~OFFSET_MASK) {
86 case BASE_BIOS:
87 memory->activeRegion = gbaMemory->bios;
88 memory->activeMask = SIZE_BIOS - 1;
89 break;
90 case BASE_WORKING_RAM:
91 memory->activeRegion = gbaMemory->wram;
92 memory->activeMask = SIZE_WORKING_RAM - 1;
93 break;
94 case BASE_WORKING_IRAM:
95 memory->activeRegion = gbaMemory->iwram;
96 memory->activeMask = SIZE_WORKING_IRAM - 1;
97 break;
98 case BASE_CART0:
99 case BASE_CART0_EX:
100 case BASE_CART1:
101 case BASE_CART1_EX:
102 case BASE_CART2:
103 case BASE_CART2_EX:
104 memory->activeRegion = gbaMemory->rom;
105 memory->activeMask = SIZE_CART0 - 1;
106 break;
107 default:
108 memory->activeRegion = 0;
109 memory->activeMask = 0;
110 break;
111 }
112}
113
114int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
115 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
116 uint32_t value = 0;
117 int wait = 0;
118
119 switch (address & ~OFFSET_MASK) {
120 case BASE_BIOS:
121 break;
122 case BASE_WORKING_RAM:
123 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
124 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
125 break;
126 case BASE_WORKING_IRAM:
127 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
128 break;
129 case BASE_IO:
130 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
131 break;
132 case BASE_PALETTE_RAM:
133 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
134 break;
135 case BASE_VRAM:
136 value = ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2];
137 break;
138 case BASE_OAM:
139 value = ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2];
140 break;
141 case BASE_CART0:
142 case BASE_CART0_EX:
143 case BASE_CART1:
144 case BASE_CART1_EX:
145 case BASE_CART2:
146 case BASE_CART2_EX:
147 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
148 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
149 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
150 }
151 break;
152 case BASE_CART_SRAM:
153 break;
154 default:
155 break;
156 }
157
158
159 if (cycleCounter) {
160 *cycleCounter += wait;
161 }
162 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
163 int rotate = (address & 3) << 3;
164 return (value >> rotate) | (value << (32 - rotate));
165}
166
167uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
168 return GBALoad16(memory, address, cycleCounter);
169}
170
171int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
172 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
173 int16_t value = 0;
174 int wait = 0;
175
176 switch (address & ~OFFSET_MASK) {
177 case BASE_BIOS:
178 break;
179 case BASE_WORKING_RAM:
180 value = ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
181 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
182 break;
183 case BASE_WORKING_IRAM:
184 value = ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
185 break;
186 case BASE_IO:
187 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
188 break;
189 case BASE_PALETTE_RAM:
190 value = gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
191 break;
192 case BASE_VRAM:
193 value = gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
194 break;
195 case BASE_OAM:
196 value = gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1];
197 break;
198 case BASE_CART0:
199 case BASE_CART0_EX:
200 case BASE_CART1:
201 case BASE_CART1_EX:
202 case BASE_CART2:
203 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
204 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
205 value = ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
206 }
207 break;
208 case BASE_CART2_EX:
209 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
210 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
211 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
212 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
213 value = ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
214 }
215 break;
216 case BASE_CART_SRAM:
217 break;
218 default:
219 break;
220 }
221
222 if (cycleCounter) {
223 *cycleCounter += wait;
224 }
225 return value;
226}
227
228uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
229 return GBALoad8(memory, address, cycleCounter);
230}
231
232int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
233 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
234 int8_t value = 0;
235 int wait = 0;
236
237 switch (address & ~OFFSET_MASK) {
238 case BASE_BIOS:
239 break;
240 case BASE_WORKING_RAM:
241 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
242 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
243 break;
244 case BASE_WORKING_IRAM:
245 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
246 break;
247 case BASE_IO:
248 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
249 break;
250 case BASE_PALETTE_RAM:
251 break;
252 case BASE_VRAM:
253 break;
254 case BASE_OAM:
255 break;
256 case BASE_CART0:
257 case BASE_CART0_EX:
258 case BASE_CART1:
259 case BASE_CART1_EX:
260 case BASE_CART2:
261 case BASE_CART2_EX:
262 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
263 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
264 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
265 }
266 break;
267 case BASE_CART_SRAM:
268 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
269 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
270 GBASavedataInitSRAM(&gbaMemory->savedata);
271 }
272 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
273 default:
274 break;
275 }
276
277 if (cycleCounter) {
278 *cycleCounter += wait;
279 }
280 return value;
281}
282
283void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
284 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
285 int wait = 0;
286
287 switch (address & ~OFFSET_MASK) {
288 case BASE_WORKING_RAM:
289 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
290 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
291 break;
292 case BASE_WORKING_IRAM:
293 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
294 break;
295 case BASE_IO:
296 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
297 break;
298 case BASE_PALETTE_RAM:
299 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
300 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
301 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
302 break;
303 case BASE_VRAM:
304 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
305 ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2] = value;
306 }
307 break;
308 case BASE_OAM:
309 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
310 break;
311 case BASE_CART0:
312 break;
313 case BASE_CART_SRAM:
314 break;
315 default:
316 break;
317 }
318
319 if (cycleCounter) {
320 *cycleCounter += wait;
321 }
322}
323
324void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
325 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
326 int wait = 0;
327
328 switch (address & ~OFFSET_MASK) {
329 case BASE_WORKING_RAM:
330 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
331 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
332 break;
333 case BASE_WORKING_IRAM:
334 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
335 break;
336 case BASE_IO:
337 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
338 break;
339 case BASE_PALETTE_RAM:
340 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
341 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
342 break;
343 case BASE_VRAM:
344 if ((address & OFFSET_MASK) < SIZE_VRAM) {
345 gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1] = value;
346 }
347 break;
348 case BASE_OAM:
349 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
350 break;
351 case BASE_CART0:
352 break;
353 case BASE_CART2_EX:
354 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
355 GBASavedataInitEEPROM(&gbaMemory->savedata);
356 }
357 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
358 break;
359 case BASE_CART_SRAM:
360 break;
361 default:
362 break;
363 }
364
365 if (cycleCounter) {
366 *cycleCounter += wait;
367 }
368}
369
370void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
371 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
372 int wait = 0;
373
374 switch (address & ~OFFSET_MASK) {
375 case BASE_WORKING_RAM:
376 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
377 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
378 break;
379 case BASE_WORKING_IRAM:
380 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
381 break;
382 case BASE_IO:
383 break;
384 case BASE_PALETTE_RAM:
385 break;
386 case BASE_VRAM:
387 break;
388 case BASE_OAM:
389 break;
390 case BASE_CART0:
391 break;
392 case BASE_CART_SRAM:
393 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
394 if (address == SAVEDATA_FLASH_BASE) {
395 GBASavedataInitFlash(&gbaMemory->savedata);
396 } else {
397 GBASavedataInitSRAM(&gbaMemory->savedata);
398 }
399 }
400 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
401 GBASavedataWriteFlash(&gbaMemory->savedata, value);
402 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
403 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
404 }
405 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
406 break;
407 default:
408 break;
409 }
410
411 if (cycleCounter) {
412 *cycleCounter += wait;
413 }
414}
415
416void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
417 int sram = parameters & 0x0003;
418 int ws0 = (parameters & 0x000C) >> 2;
419 int ws0seq = (parameters & 0x0010) >> 4;
420 int ws1 = (parameters & 0x0060) >> 5;
421 int ws1seq = (parameters & 0x0080) >> 7;
422 int ws2 = (parameters & 0x0300) >> 8;
423 int ws2seq = (parameters & 0x0400) >> 10;
424 int prefetch = parameters & 0x4000;
425
426 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
427 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
428 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
429 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
430
431 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
432 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
433 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
434
435 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
436 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
437 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
438
439 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
440 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
441 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
442
443 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
444 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
445 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
446
447 if (!prefetch) {
448 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
449 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
450 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
451
452 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
453 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
454 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
455 } else {
456 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
457 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
458 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
459
460 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
461 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
462 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
463 }
464
465 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
466 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
467}
468
469int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
470 struct GBADMA* dma;
471 int32_t test = INT_MAX;
472
473 dma = &memory->dma[0];
474 dma->nextIRQ -= cycles;
475 if (dma->enable && dma->doIrq && dma->nextIRQ) {
476 if (dma->nextIRQ <= 0) {
477 dma->nextIRQ = INT_MAX;
478 GBARaiseIRQ(memory->p, IRQ_DMA0);
479 } else if (dma->nextIRQ < test) {
480 test = dma->nextIRQ;
481 }
482 }
483
484 dma = &memory->dma[1];
485 dma->nextIRQ -= cycles;
486 if (dma->enable && dma->doIrq && dma->nextIRQ) {
487 if (dma->nextIRQ <= 0) {
488 dma->nextIRQ = INT_MAX;
489 GBARaiseIRQ(memory->p, IRQ_DMA1);
490 } else if (dma->nextIRQ < test) {
491 test = dma->nextIRQ;
492 }
493 }
494
495 dma = &memory->dma[2];
496 dma->nextIRQ -= cycles;
497 if (dma->enable && dma->doIrq && dma->nextIRQ) {
498 if (dma->nextIRQ <= 0) {
499 dma->nextIRQ = INT_MAX;
500 GBARaiseIRQ(memory->p, IRQ_DMA2);
501 } else if (dma->nextIRQ < test) {
502 test = dma->nextIRQ;
503 }
504 }
505
506 dma = &memory->dma[3];
507 dma->nextIRQ -= cycles;
508 if (dma->enable && dma->doIrq && dma->nextIRQ) {
509 if (dma->nextIRQ <= 0) {
510 dma->nextIRQ = INT_MAX;
511 GBARaiseIRQ(memory->p, IRQ_DMA3);
512 } else if (dma->nextIRQ < test) {
513 test = dma->nextIRQ;
514 }
515 }
516
517 return test;
518}
519
520void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
521 memory->dma[dma].source = address & 0xFFFFFFFE;
522}
523
524void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
525 memory->dma[dma].dest = address & 0xFFFFFFFE;
526}
527
528void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
529 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
530}
531
532uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
533 struct GBADMA* currentDma = &memory->dma[dma];
534 int wasEnabled = currentDma->enable;
535 currentDma->packed = control;
536 currentDma->nextIRQ = 0;
537
538 if (currentDma->drq) {
539 GBALog(GBA_LOG_STUB, "DRQ not implemented");
540 }
541
542 if (!wasEnabled && currentDma->enable) {
543 currentDma->nextSource = currentDma->source;
544 currentDma->nextDest = currentDma->dest;
545 currentDma->nextCount = currentDma->count;
546 GBAMemoryScheduleDMA(memory, dma, currentDma);
547 }
548 // If the DMA has already occurred, this value might have changed since the function started
549 return currentDma->packed;
550};
551
552void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
553 switch (info->timing) {
554 case DMA_TIMING_NOW:
555 GBAMemoryServiceDMA(memory, number, info);
556 break;
557 case DMA_TIMING_HBLANK:
558 // Handled implicitly
559 break;
560 case DMA_TIMING_VBLANK:
561 // Handled implicitly
562 break;
563 case DMA_TIMING_CUSTOM:
564 switch (number) {
565 case 0:
566 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
567 break;
568 case 1:
569 case 2:
570 //this.cpu.irq.audio.scheduleFIFODma(number, info);
571 break;
572 case 3:
573 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
574 break;
575 }
576 }
577}
578
579void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
580 struct GBADMA* dma;
581 int i;
582 for (i = 0; i < 4; ++i) {
583 dma = &memory->dma[i];
584 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
585 GBAMemoryServiceDMA(memory, i, dma);
586 }
587 }
588}
589
590void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
591 struct GBADMA* dma;
592 int i;
593 for (i = 0; i < 4; ++i) {
594 dma = &memory->dma[i];
595 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
596 GBAMemoryServiceDMA(memory, i, dma);
597 }
598 }
599}
600
601void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
602 if (!info->enable) {
603 // There was a DMA scheduled that got canceled
604 return;
605 }
606
607 uint32_t width = info->width ? 4 : 2;
608 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
609 int destOffset = DMA_OFFSET[info->dstControl] * width;
610 int32_t wordsRemaining = info->nextCount;
611 uint32_t source = info->nextSource;
612 uint32_t dest = info->nextDest;
613 uint32_t sourceRegion = source >> BASE_OFFSET;
614 uint32_t destRegion = dest >> BASE_OFFSET;
615
616 if (width == 4) {
617 int32_t word;
618 source &= 0xFFFFFFFC;
619 dest &= 0xFFFFFFFC;
620 while (wordsRemaining--) {
621 word = GBALoad32(&memory->d, source, 0);
622 GBAStore32(&memory->d, dest, word, 0);
623 source += sourceOffset;
624 dest += destOffset;
625 }
626 } else {
627 uint16_t word;
628 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
629 while (wordsRemaining--) {
630 word = GBASavedataReadEEPROM(&memory->savedata);
631 GBAStore16(&memory->d, dest, word, 0);
632 source += sourceOffset;
633 dest += destOffset;
634 }
635 } else if (destRegion == REGION_CART2_EX) {
636 if (memory->savedata.type != SAVEDATA_EEPROM) {
637 GBASavedataInitEEPROM(&memory->savedata);
638 }
639 while (wordsRemaining) {
640 word = GBALoadU16(&memory->d, source, 0);
641 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
642 source += sourceOffset;
643 dest += destOffset;
644 --wordsRemaining;
645 }
646 } else {
647 while (wordsRemaining--) {
648 word = GBALoadU16(&memory->d, source, 0);
649 GBAStore16(&memory->d, dest, word, 0);
650 source += sourceOffset;
651 dest += destOffset;
652 }
653 }
654 }
655
656 if (info->doIrq) {
657 info->nextIRQ = memory->p->cpu.cycles + 2;
658 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
659 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
660 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
661 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
662 }
663
664 info->nextSource = source;
665 info->nextDest = dest;
666 info->nextCount = wordsRemaining;
667
668 if (!info->repeat) {
669 info->enable = 0;
670
671 // Clear the enable bit in memory
672 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
673 } else {
674 info->nextCount = info->count;
675 if (info->dstControl == DMA_INCREMENT_RELOAD) {
676 info->nextDest = info->dest;
677 }
678 GBAMemoryScheduleDMA(memory, number, info);
679 }
680}