1#ifndef ARM_DECODER_H
  2#define ARM_DECODER_H
  3
  4#include "arm.h"
  5
  6// Bit 0: a register is involved with this operand
  7// Bit 1: an immediate is invovled with this operand
  8// Bit 2: a memory access is invovled with this operand
  9// Bit 3: the destination of this operand is affected by this opcode
 10// Bit 4: this operand is shifted by a register
 11// Bit 5: this operand is shifted by an immediate
 12#define ARM_OPERAND_NONE                0x00000000
 13#define ARM_OPERAND_REGISTER_1          0x00000001
 14#define ARM_OPERAND_IMMEDIATE_1         0x00000002
 15#define ARM_OPERAND_MEMORY_1            0x00000004
 16#define ARM_OPERAND_AFFECTED_1          0x00000008
 17#define ARM_OPERAND_SHIFT_REGISTER_1    0x00000010
 18#define ARM_OPERAND_SHIFT_IMMEDIATE_1   0x00000020
 19#define ARM_OPERAND_1                   0x000000FF
 20
 21#define ARM_OPERAND_REGISTER_2          0x00000100
 22#define ARM_OPERAND_IMMEDIATE_2         0x00000200
 23#define ARM_OPERAND_MEMORY_2            0x00000400
 24#define ARM_OPERAND_AFFECTED_2          0x00000800
 25#define ARM_OPERAND_SHIFT_REGISTER_2    0x00001000
 26#define ARM_OPERAND_SHIFT_IMMEDIATE_2   0x00002000
 27#define ARM_OPERAND_2                   0x0000FF00
 28
 29#define ARM_OPERAND_REGISTER_3          0x00010000
 30#define ARM_OPERAND_IMMEDIATE_3         0x00020000
 31#define ARM_OPERAND_MEMORY_3            0x00040000
 32#define ARM_OPERAND_AFFECTED_3          0x00080000
 33#define ARM_OPERAND_SHIFT_REGISTER_3    0x00100000
 34#define ARM_OPERAND_SHIFT_IMMEDIATE_3   0x00200000
 35#define ARM_OPERAND_3                   0x00FF0000
 36
 37#define ARM_OPERAND_REGISTER_4          0x01000000
 38#define ARM_OPERAND_IMMEDIATE_4         0x02000000
 39#define ARM_OPERAND_MEMORY_4            0x04000000
 40#define ARM_OPERAND_AFFECTED_4          0x08000000
 41#define ARM_OPERAND_SHIFT_REGISTER_4    0x10000000
 42#define ARM_OPERAND_SHIFT_IMMEDIATE_4   0x20000000
 43#define ARM_OPERAND_4                   0xFF000000
 44
 45
 46#define ARM_MEMORY_REGISTER_BASE     0x0001
 47#define ARM_MEMORY_IMMEDIATE_OFFSET  0x0002
 48#define ARM_MEMORY_REGISTER_OFFSET   0x0004
 49#define ARM_MEMORY_SHIFTED_OFFSET    0x0008
 50#define ARM_MEMORY_PRE_INCREMENT     0x0010
 51#define ARM_MEMORY_POST_INCREMENT    0x0020
 52#define ARM_MEMORY_OFFSET_SUBTRACT   0x0040
 53#define ARM_MEMORY_WRITEBACK         0x0080
 54#define ARM_MEMORY_DECREMENT_AFTER   0x0000
 55#define ARM_MEMORY_INCREMENT_AFTER   0x0100
 56#define ARM_MEMORY_DECREMENT_BEFORE  0x0200
 57#define ARM_MEMORY_INCREMENT_BEFORE  0x0300
 58
 59#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x7)
 60
 61enum ARMCondition {
 62	ARM_CONDITION_EQ = 0x0,
 63	ARM_CONDITION_NE = 0x1,
 64	ARM_CONDITION_CS = 0x2,
 65	ARM_CONDITION_CC = 0x3,
 66	ARM_CONDITION_MI = 0x4,
 67	ARM_CONDITION_PL = 0x5,
 68	ARM_CONDITION_VS = 0x6,
 69	ARM_CONDITION_VC = 0x7,
 70	ARM_CONDITION_HI = 0x8,
 71	ARM_CONDITION_LS = 0x9,
 72	ARM_CONDITION_GE = 0xA,
 73	ARM_CONDITION_LT = 0xB,
 74	ARM_CONDITION_GT = 0xC,
 75	ARM_CONDITION_LE = 0xD,
 76	ARM_CONDITION_AL = 0xE,
 77	ARM_CONDITION_NV = 0xF
 78};
 79
 80enum ARMShifterOperation {
 81	ARM_SHIFT_NONE = 0,
 82	ARM_SHIFT_LSL,
 83	ARM_SHIFT_LSR,
 84	ARM_SHIFT_ASR,
 85	ARM_SHIFT_ROR,
 86	ARM_SHIFT_RRX
 87};
 88
 89union ARMOperand {
 90	struct {
 91		uint8_t reg;
 92		enum ARMShifterOperation shifterOp;
 93		union {
 94			uint8_t shifterReg;
 95			uint8_t shifterImm;
 96		};
 97	};
 98	int32_t immediate;
 99};
100
101enum ARMMemoryAccessType {
102	ARM_ACCESS_WORD = 4,
103	ARM_ACCESS_HALFWORD = 2,
104	ARM_ACCESS_SIGNED_HALFWORD = 10,
105	ARM_ACCESS_BYTE = 1,
106	ARM_ACCESS_SIGNED_BYTE = 9,
107	ARM_ACCESS_TRANSLATED_WORD = 20,
108	ARM_ACCESS_TRANSLATED_BYTE = 17
109};
110
111struct ARMMemoryAccess {
112	uint8_t baseReg;
113	uint16_t format;
114	union ARMOperand offset;
115	enum ARMMemoryAccessType width;
116};
117
118enum ARMMnemonic {
119	ARM_MN_ILL = 0,
120	ARM_MN_ADC,
121	ARM_MN_ADD,
122	ARM_MN_AND,
123	ARM_MN_ASR,
124	ARM_MN_B,
125	ARM_MN_BIC,
126	ARM_MN_BKPT,
127	ARM_MN_BL,
128	ARM_MN_BLH,
129	ARM_MN_BX,
130	ARM_MN_CMN,
131	ARM_MN_CMP,
132	ARM_MN_EOR,
133	ARM_MN_LDM,
134	ARM_MN_LDR,
135	ARM_MN_LSL,
136	ARM_MN_LSR,
137	ARM_MN_MLA,
138	ARM_MN_MOV,
139	ARM_MN_MRS,
140	ARM_MN_MSR,
141	ARM_MN_MUL,
142	ARM_MN_MVN,
143	ARM_MN_NEG,
144	ARM_MN_ORR,
145	ARM_MN_ROR,
146	ARM_MN_RSB,
147	ARM_MN_RSC,
148	ARM_MN_SBC,
149	ARM_MN_SMLAL,
150	ARM_MN_SMULL,
151	ARM_MN_STM,
152	ARM_MN_STR,
153	ARM_MN_SUB,
154	ARM_MN_SWI,
155	ARM_MN_SWP,
156	ARM_MN_TEQ,
157	ARM_MN_TST,
158	ARM_MN_UMLAL,
159	ARM_MN_UMULL,
160
161	ARM_MN_MAX
162};
163
164enum {
165	ARM_CPSR = 16,
166	ARM_SPSR = 17
167};
168
169struct ARMInstructionInfo {
170	enum ExecutionMode execMode;
171	uint32_t opcode;
172	enum ARMMnemonic mnemonic;
173	union ARMOperand op1;
174	union ARMOperand op2;
175	union ARMOperand op3;
176	union ARMOperand op4;
177	struct ARMMemoryAccess memory;
178	int operandFormat;
179	int branches;
180	int traps;
181	int affectsCPSR;
182	int condition;
183	int sDataCycles;
184	int nDataCycles;
185	int sInstructionCycles;
186	int nInstructionCycles;
187	int iCycles;
188	int cCycles;
189};
190
191void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
192void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
193int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
194
195#endif