src/arm.c (view raw)
1#include "arm.h"
2
3static inline void _ARMSetMode(struct ARMCore*, enum ExecutionMode);
4static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
5static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
6
7static inline void _ARMReadCPSR(struct ARMCore* cpu) {
8 _ARMSetMode(cpu, cpu->cpsr.t);
9}
10
11static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
12 return mode != MODE_SYSTEM && mode != MODE_USER;
13}
14
15static const ARMInstruction armTable[0xF000];
16
17static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
18 if (executionMode == cpu->executionMode) {
19 return;
20 }
21
22 cpu->executionMode = executionMode;
23 switch (executionMode) {
24 case MODE_ARM:
25 cpu->cpsr.t = 0;
26 cpu->instructionWidth = WORD_SIZE_ARM;
27 cpu->loadInstruction = _ARMLoadInstructionARM;
28 break;
29 case MODE_THUMB:
30 cpu->cpsr.t = 1;
31 cpu->instructionWidth = WORD_SIZE_THUMB;
32 cpu->loadInstruction = _ARMLoadInstructionThumb;
33 }
34}
35
36static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
37 uint32_t opcode = memory->load32(memory, address);
38 *opcodeOut = opcode;
39 return 0;
40}
41
42static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
43 uint16_t opcode = memory->loadU16(memory, address);
44 *opcodeOut = opcode;
45 return 0;
46}
47
48void ARMInit(struct ARMCore* cpu) {
49 int i;
50 for (i = 0; i < 16; ++i) {
51 cpu->gprs[i] = 0;
52 }
53
54 cpu->cpsr.packed = MODE_SYSTEM;
55 cpu->spsr.packed = 0;
56
57 cpu->cyclesToEvent = 0;
58
59 cpu->shifterOperand = 0;
60 cpu->shifterCarryOut = 0;
61
62 cpu->memory = 0;
63 cpu->board = 0;
64
65 cpu->executionMode = MODE_THUMB;
66 _ARMSetMode(cpu, MODE_ARM);
67}
68
69void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory) {
70 cpu->memory = memory;
71}
72
73inline void ARMCycle(struct ARMCore* cpu) {
74 // TODO
75 uint32_t opcode;
76 ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth, &opcode);
77 cpu->gprs[ARM_PC] += cpu->instructionWidth;
78 instruction(cpu, opcode);
79}
80
81// Instruction definitions
82// Beware pre-processor antics
83
84#define ARM_CARRY_FROM(M, N, D) ((((M) | (N)) >> 31) && !((D) >> 31))
85#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
86#define ARM_V_ADDITION(M, N, D) (!(((M) ^ (N)) >> 31) && (((M) ^ (D)) >> 31) && (((N) ^ (D)) >> 31))
87#define ARM_V_SUBTRACTION(M, N, D) ((((M) ^ (N)) >> 31) && (((M) ^ (D)) >> 31))
88
89#define ARM_COND_EQ (cpu->cpsr.z)
90#define ARM_COND_NE (!cpu->cpsr.z)
91#define ARM_COND_CS (cpu->cpsr.c)
92#define ARM_COND_CC (!cpu->cpsr.c)
93#define ARM_COND_MI (cpu->cpsr.n)
94#define ARM_COND_PL (!cpu->cpsr.n)
95#define ARM_COND_VS (cpu->cpsr.v)
96#define ARM_COND_VC (!cpu->cpsr.v)
97#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
98#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
99#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
100#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
101#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
102#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
103#define ARM_COND_AL 1
104
105#define ARM_ADDITION_S(M, N, D) \
106 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
107 cpu->cpsr = cpu->spsr; \
108 _ARMReadCPSR(cpu); \
109 } else { \
110 cpu->cpsr.n = (D) >> 31; \
111 cpu->cpsr.z = !(D); \
112 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
113 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
114 }
115
116#define ARM_SUBTRACTION_S(M, N, D) \
117 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
118 cpu->cpsr = cpu->spsr; \
119 _ARMReadCPSR(cpu); \
120 } else { \
121 cpu->cpsr.n = (D) >> 31; \
122 cpu->cpsr.z = !(D); \
123 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
124 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
125 }
126
127#define ARM_NEUTRAL_S(M, N, D) \
128 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
129 cpu->cpsr = cpu->spsr; \
130 _ARMReadCPSR(cpu); \
131 } else { \
132 cpu->cpsr.n = (D) >> 31; \
133 cpu->cpsr.z = !(D); \
134 cpu->cpsr.c = cpu->shifterCarryOut; \
135 }
136
137// TODO: shifter
138#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, S, S_BODY, BODY, POST_BODY) \
139 static void _ARMInstruction ## NAME ## S ## COND (struct ARMCore* cpu, uint32_t opcode) { \
140 if (!COND_BODY) { \
141 return; \
142 } \
143 int rd = (opcode >> 12) & 0xF; \
144 int rn = (opcode >> 16) & 0xF; \
145 BODY; \
146 S_BODY; \
147 POST_BODY; \
148 }
149
150#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
151 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, , , BODY, POST_BODY) \
152 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, , , BODY, POST_BODY) \
153 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, , , BODY, POST_BODY) \
154 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, , , BODY, POST_BODY) \
155 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, , , BODY, POST_BODY) \
156 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, , , BODY, POST_BODY) \
157 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, , , BODY, POST_BODY) \
158 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, , , BODY, POST_BODY) \
159 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, , , BODY, POST_BODY) \
160 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, , , BODY, POST_BODY) \
161 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, , , BODY, POST_BODY) \
162 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, , , BODY, POST_BODY) \
163 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, , , BODY, POST_BODY) \
164 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, , , BODY, POST_BODY) \
165 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, , , BODY, POST_BODY) \
166 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, S, S_BODY, BODY, POST_BODY) \
167 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, S, S_BODY, BODY, POST_BODY) \
168 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, S, S_BODY, BODY, POST_BODY) \
169 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, S, S_BODY, BODY, POST_BODY) \
170 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, S, S_BODY, BODY, POST_BODY) \
171 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, S, S_BODY, BODY, POST_BODY) \
172 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, S, S_BODY, BODY, POST_BODY) \
173 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, S, S_BODY, BODY, POST_BODY) \
174 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, S, S_BODY, BODY, POST_BODY) \
175 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, S, S_BODY, BODY, POST_BODY) \
176 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, S, S_BODY, BODY, POST_BODY) \
177 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, S, S_BODY, BODY, POST_BODY) \
178 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, S, S_BODY, BODY, POST_BODY) \
179 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, S, S_BODY, BODY, POST_BODY) \
180 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, S, S_BODY, BODY, POST_BODY)
181
182// Begin ALU definitions
183
184DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
185 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
186
187DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
188 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
189 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
190
191DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
192 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
193
194DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
195 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
196
197DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
198 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
199
200DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
201 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
202 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
203
204DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
205 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
206 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
207
208DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
209 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
210
211// End ALU definitions
212
213#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
214 _ARMInstruction ## NAME ## COND
215
216#define DO_8(DIRECTIVE) \
217 DIRECTIVE, \
218 DIRECTIVE, \
219 DIRECTIVE, \
220 DIRECTIVE, \
221 DIRECTIVE, \
222 DIRECTIVE, \
223 DIRECTIVE, \
224 DIRECTIVE, \
225 DIRECTIVE, \
226 DIRECTIVE \
227
228// TODO: MUL
229#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
230 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
231 DECLARE_INSTRUCTION_ARM(COND, ALU), \
232 0, \
233 DECLARE_INSTRUCTION_ARM(COND, ALU), \
234 0, \
235 DECLARE_INSTRUCTION_ARM(COND, ALU), \
236 0, \
237 DECLARE_INSTRUCTION_ARM(COND, ALU), \
238 0
239
240#define DECLARE_COND_BLOCK(COND) \
241 DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, 0, 0), \
242 DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
243 DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, 0, 0), \
244 DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH), \
245 DECLARE_ARM_ALU_BLOCK(COND, SUB, 0, STRH, 0, 0), \
246 DECLARE_ARM_ALU_BLOCK(COND, SUBS, 0, LDRH, LDRSB, LDRSH), \
247 DECLARE_ARM_ALU_BLOCK(COND, RSB, 0, STRH, 0, 0), \
248 DECLARE_ARM_ALU_BLOCK(COND, RSBS, 0, LDRH, LDRSB, LDRSH), \
249 DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, 0, 0), \
250 DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
251 DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, 0, 0), \
252 DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
253 DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
254 DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
255 DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
256 DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH)
257
258static const ARMInstruction armTable[0xF000] = {
259 DECLARE_COND_BLOCK(EQ),
260 DECLARE_COND_BLOCK(NE),
261 DECLARE_COND_BLOCK(CS),
262 DECLARE_COND_BLOCK(CC),
263 DECLARE_COND_BLOCK(MI),
264 DECLARE_COND_BLOCK(PL),
265 DECLARE_COND_BLOCK(VS),
266 DECLARE_COND_BLOCK(VC),
267 DECLARE_COND_BLOCK(HI),
268 DECLARE_COND_BLOCK(LS),
269 DECLARE_COND_BLOCK(GE),
270 DECLARE_COND_BLOCK(LT),
271 DECLARE_COND_BLOCK(GT),
272 DECLARE_COND_BLOCK(LE),
273 DECLARE_COND_BLOCK(AL)
274};