1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_VRAM = 0x8000,
 26	GB_BASE_EXTERNAL_RAM = 0xA000,
 27	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 28	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 29	GB_BASE_OAM = 0xFE00,
 30	GB_BASE_UNUSABLE = 0xFEA0,
 31	GB_BASE_IO = 0xFF00,
 32	GB_BASE_HRAM = 0xFF80,
 33	GB_BASE_IE = 0xFFFF
 34};
 35
 36enum {
 37	GB_REGION_CART_BANK0 = 0x0,
 38	GB_REGION_CART_BANK1 = 0x4,
 39	GB_REGION_VRAM = 0x8,
 40	GB_REGION_EXTERNAL_RAM = 0xA,
 41	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 42	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 43	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 44	GB_REGION_OTHER = 0xF,
 45};
 46
 47enum {
 48	GB_SIZE_CART_BANK0 = 0x4000,
 49	GB_SIZE_CART_MAX = 0x800000,
 50	GB_SIZE_VRAM = 0x4000,
 51	GB_SIZE_VRAM_BANK0 = 0x2000,
 52	GB_SIZE_EXTERNAL_RAM = 0x2000,
 53	GB_SIZE_WORKING_RAM = 0x8000,
 54	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 55	GB_SIZE_OAM = 0xA0,
 56	GB_SIZE_IO = 0x80,
 57	GB_SIZE_HRAM = 0x7F,
 58};
 59
 60enum {
 61	GB_SRAM_DIRT_NEW = 1,
 62	GB_SRAM_DIRT_SEEN = 2
 63};
 64
 65struct GBMemory;
 66typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
 67typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
 68
 69DECL_BITFIELD(GBMBC7Field, uint8_t);
 70DECL_BIT(GBMBC7Field, CS, 7);
 71DECL_BIT(GBMBC7Field, CLK, 6);
 72DECL_BIT(GBMBC7Field, DI, 1);
 73DECL_BIT(GBMBC7Field, DO, 0);
 74
 75enum GBMBC7MachineState {
 76	GBMBC7_STATE_IDLE = 0,
 77	GBMBC7_STATE_READ_COMMAND = 1,
 78	GBMBC7_STATE_DO = 2,
 79
 80	GBMBC7_STATE_EEPROM_EWDS = 0x10,
 81	GBMBC7_STATE_EEPROM_WRAL = 0x11,
 82	GBMBC7_STATE_EEPROM_ERAL = 0x12,
 83	GBMBC7_STATE_EEPROM_EWEN = 0x13,
 84	GBMBC7_STATE_EEPROM_WRITE = 0x14,
 85	GBMBC7_STATE_EEPROM_READ = 0x18,
 86	GBMBC7_STATE_EEPROM_ERASE = 0x1C,
 87};
 88
 89enum GBTAMA5Register {
 90	GBTAMA5_BANK = 0x0,
 91	GBTAMA5_MAX
 92};
 93
 94struct GBMBC1State {
 95	int mode;
 96	int multicartStride;
 97};
 98
 99struct GBMBC7State {
100	enum GBMBC7MachineState state;
101	uint16_t sr;
102	uint8_t address;
103	bool writable;
104	int srBits;
105	uint8_t access;
106	uint8_t latch;
107	GBMBC7Field eeprom;
108};
109
110struct GBPocketCamState {
111	bool registersActive;
112};
113
114struct GBTAMA5State {
115	bool unlocked;
116	uint8_t reg;
117	uint8_t value;
118	uint8_t registers[GBTAMA5_MAX];
119};
120
121union GBMBCState {
122	struct GBMBC1State mbc1;
123	struct GBMBC7State mbc7;
124	struct GBPocketCamState pocketCam;
125	struct GBTAMA5State tama5;
126};
127
128struct mRotationSource;
129struct GBMemory {
130	uint8_t* rom;
131	uint8_t* romBase;
132	uint8_t* romBank;
133	enum GBMemoryBankControllerType mbcType;
134	GBMemoryBankControllerWrite mbcWrite;
135	GBMemoryBankControllerRead mbcRead;
136	union GBMBCState mbcState;
137	int currentBank;
138
139	uint8_t* wram;
140	uint8_t* wramBank;
141	int wramCurrentBank;
142
143	bool sramAccess;
144	uint8_t* sram;
145	uint8_t* sramBank;
146	int sramCurrentBank;
147
148	uint8_t io[GB_SIZE_IO];
149	bool ime;
150	uint8_t ie;
151
152	uint8_t hram[GB_SIZE_HRAM];
153
154	uint16_t dmaSource;
155	uint16_t dmaDest;
156	int dmaRemaining;
157
158	uint16_t hdmaSource;
159	uint16_t hdmaDest;
160	int hdmaRemaining;
161	bool isHdma;
162
163	struct mTimingEvent dmaEvent;
164	struct mTimingEvent hdmaEvent;
165
166	size_t romSize;
167
168	bool rtcAccess;
169	int activeRtcReg;
170	bool rtcLatched;
171	uint8_t rtcRegs[5];
172	time_t rtcLastLatch;
173	struct mRTCSource* rtc;
174	struct mRotationSource* rotation;
175	struct mRumble* rumble;
176};
177
178struct LR35902Core;
179void GBMemoryInit(struct GB* gb);
180void GBMemoryDeinit(struct GB* gb);
181
182void GBMemoryReset(struct GB* gb);
183void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
184
185uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
186void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
187
188int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
189
190uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
191
192void GBMemoryDMA(struct GB* gb, uint16_t base);
193void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
194
195void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
196
197struct GBSerializedState;
198void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
199void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
200
201CXX_GUARD_END
202
203#endif