src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5#include "emitter-inlines.h"
6
7enum {
8 PSR_USER_MASK = 0xF0000000,
9 PSR_PRIV_MASK = 0x000000CF,
10 PSR_STATE_MASK = 0x00000020
11};
12
13// Addressing mode 1
14static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
15 int rm = opcode & 0x0000000F;
16 int immediate = (opcode & 0x00000F80) >> 7;
17 if (!immediate) {
18 cpu->shifterOperand = cpu->gprs[rm];
19 cpu->shifterCarryOut = cpu->cpsr.c;
20 } else {
21 cpu->shifterOperand = cpu->gprs[rm] << immediate;
22 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
23 }
24}
25
26static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
27 int rm = opcode & 0x0000000F;
28 int rs = (opcode >> 8) & 0x0000000F;
29 ++cpu->cycles;
30 int shift = cpu->gprs[rs];
31 if (rs == ARM_PC) {
32 shift += 4;
33 }
34 shift &= 0xFF;
35 int32_t shiftVal = cpu->gprs[rm];
36 if (rm == ARM_PC) {
37 shiftVal += 4;
38 }
39 if (!shift) {
40 cpu->shifterOperand = shiftVal;
41 cpu->shifterCarryOut = cpu->cpsr.c;
42 } else if (shift < 32) {
43 cpu->shifterOperand = shiftVal << shift;
44 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
45 } else if (shift == 32) {
46 cpu->shifterOperand = 0;
47 cpu->shifterCarryOut = shiftVal & 1;
48 } else {
49 cpu->shifterOperand = 0;
50 cpu->shifterCarryOut = 0;
51 }
52}
53
54static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
55 int rm = opcode & 0x0000000F;
56 int immediate = (opcode & 0x00000F80) >> 7;
57 if (immediate) {
58 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
59 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
60 } else {
61 cpu->shifterOperand = 0;
62 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
63 }
64}
65
66static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
67 int rm = opcode & 0x0000000F;
68 int rs = (opcode >> 8) & 0x0000000F;
69 ++cpu->cycles;
70 int shift = cpu->gprs[rs];
71 if (rs == ARM_PC) {
72 shift += 4;
73 }
74 shift &= 0xFF;
75 uint32_t shiftVal = cpu->gprs[rm];
76 if (rm == ARM_PC) {
77 shiftVal += 4;
78 }
79 if (!shift) {
80 cpu->shifterOperand = shiftVal;
81 cpu->shifterCarryOut = cpu->cpsr.c;
82 } else if (shift < 32) {
83 cpu->shifterOperand = shiftVal >> shift;
84 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
85 } else if (shift == 32) {
86 cpu->shifterOperand = 0;
87 cpu->shifterCarryOut = shiftVal >> 31;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = 0;
91 }
92}
93
94static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
95 int rm = opcode & 0x0000000F;
96 int immediate = (opcode & 0x00000F80) >> 7;
97 if (immediate) {
98 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
99 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
100 } else {
101 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
102 cpu->shifterOperand = cpu->shifterCarryOut;
103 }
104}
105
106static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
107 int rm = opcode & 0x0000000F;
108 int rs = (opcode >> 8) & 0x0000000F;
109 ++cpu->cycles;
110 int shift = cpu->gprs[rs];
111 if (rs == ARM_PC) {
112 shift += 4;
113 }
114 shift &= 0xFF;
115 int shiftVal = cpu->gprs[rm];
116 if (rm == ARM_PC) {
117 shiftVal += 4;
118 }
119 if (!shift) {
120 cpu->shifterOperand = shiftVal;
121 cpu->shifterCarryOut = cpu->cpsr.c;
122 } else if (shift < 32) {
123 cpu->shifterOperand = shiftVal >> shift;
124 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
125 } else if (cpu->gprs[rm] >> 31) {
126 cpu->shifterOperand = 0xFFFFFFFF;
127 cpu->shifterCarryOut = 1;
128 } else {
129 cpu->shifterOperand = 0;
130 cpu->shifterCarryOut = 0;
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 int immediate = (opcode & 0x00000F80) >> 7;
137 if (immediate) {
138 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
139 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
140 } else {
141 // RRX
142 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
143 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
144 }
145}
146
147static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
148 int rm = opcode & 0x0000000F;
149 int rs = (opcode >> 8) & 0x0000000F;
150 ++cpu->cycles;
151 int shift = cpu->gprs[rs];
152 if (rs == ARM_PC) {
153 shift += 4;
154 }
155 shift &= 0xFF;
156 int shiftVal = cpu->gprs[rm];
157 if (rm == ARM_PC) {
158 shiftVal += 4;
159 }
160 int rotate = shift & 0x1F;
161 if (!shift) {
162 cpu->shifterOperand = shiftVal;
163 cpu->shifterCarryOut = cpu->cpsr.c;
164 } else if (rotate) {
165 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
166 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
167 } else {
168 cpu->shifterOperand = shiftVal;
169 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ARM_ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
189
190#define ARM_ADDITION_S(M, N, D) \
191 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
192 cpu->cpsr = cpu->spsr; \
193 _ARMReadCPSR(cpu); \
194 } else { \
195 cpu->cpsr.n = ARM_SIGN(D); \
196 cpu->cpsr.z = !(D); \
197 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
198 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
199 }
200
201#define ARM_SUBTRACTION_S(M, N, D) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 cpu->cpsr.n = ARM_SIGN(D); \
207 cpu->cpsr.z = !(D); \
208 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
209 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
210 }
211
212#define ARM_NEUTRAL_S(M, N, D) \
213 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
214 cpu->cpsr = cpu->spsr; \
215 _ARMReadCPSR(cpu); \
216 } else { \
217 cpu->cpsr.n = ARM_SIGN(D); \
218 cpu->cpsr.z = !(D); \
219 cpu->cpsr.c = cpu->shifterCarryOut; \
220 }
221
222#define ARM_NEUTRAL_HI_S(DLO, DHI) \
223 cpu->cpsr.n = ARM_SIGN(DHI); \
224 cpu->cpsr.z = !((DHI) | (DLO));
225
226#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
227#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
228#define ADDR_MODE_2_ADDRESS (address)
229#define ADDR_MODE_2_RN (cpu->gprs[rn])
230#define ADDR_MODE_2_RM (cpu->gprs[rm])
231#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
232#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
233#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
234#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
235#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
236#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
237#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
238
239#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
240#define ADDR_MODE_3_RN ADDR_MODE_2_RN
241#define ADDR_MODE_3_RM ADDR_MODE_2_RM
242#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
243#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
244#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
245
246#define ARM_LOAD_POST_BODY \
247 if (rd == ARM_PC) { \
248 ARM_WRITE_PC; \
249 }
250
251#define ARM_STORE_POST_BODY \
252 currentCycles -= ARM_PREFETCH_CYCLES; \
253 currentCycles += 1 + cpu->memory->activeNonseqCycles32;
254
255#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
256 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
257 int currentCycles = ARM_PREFETCH_CYCLES; \
258 BODY; \
259 cpu->cycles += currentCycles; \
260 }
261
262#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
263 DEFINE_INSTRUCTION_ARM(NAME, \
264 int rd = (opcode >> 12) & 0xF; \
265 int rn = (opcode >> 16) & 0xF; \
266 UNUSED(rn); \
267 SHIFTER(cpu, opcode); \
268 BODY; \
269 S_BODY; \
270 if (rd == ARM_PC) { \
271 if (cpu->executionMode == MODE_ARM) { \
272 ARM_WRITE_PC; \
273 } else { \
274 THUMB_WRITE_PC; \
275 } \
276 })
277
278#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
297
298#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
308
309#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
310 DEFINE_INSTRUCTION_ARM(NAME, \
311 int rd = (opcode >> 12) & 0xF; \
312 int rdHi = (opcode >> 16) & 0xF; \
313 int rs = (opcode >> 8) & 0xF; \
314 int rm = opcode & 0xF; \
315 UNUSED(rdHi); \
316 ARM_WAIT_MUL(cpu->gprs[rs]); \
317 BODY; \
318 S_BODY; \
319 if (rd == ARM_PC) { \
320 ARM_WRITE_PC; \
321 })
322
323#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
324 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
325 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
326
327#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
328 DEFINE_INSTRUCTION_ARM(NAME, \
329 uint32_t address; \
330 int rn = (opcode >> 16) & 0xF; \
331 int rd = (opcode >> 12) & 0xF; \
332 int rm = opcode & 0xF; \
333 UNUSED(rm); \
334 address = ADDRESS; \
335 WRITEBACK; \
336 BODY;)
337
338#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
344 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
345
346#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
357
358#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
371
372#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
375
376#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
377 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
378 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
379 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
380 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
383
384#define ARM_MS_PRE \
385 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
386 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
387
388#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
389
390#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
391#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
392#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
393#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
394#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
395#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
396#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
397#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
398
399#define ARM_M_INCREMENT(BODY) \
400 for (m = rs, i = 0; m; m >>= 1, ++i) { \
401 if (m & 1) { \
402 BODY; \
403 addr += 4; \
404 total += 1; \
405 } \
406 }
407
408#define ARM_M_DECREMENT(BODY) \
409 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
410 if (rs & m) { \
411 BODY; \
412 addr -= 4; \
413 total += 1; \
414 } \
415 }
416
417#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
418 DEFINE_INSTRUCTION_ARM(NAME, \
419 int rn = (opcode >> 16) & 0xF; \
420 int rs = opcode & 0x0000FFFF; \
421 int m; \
422 int i; \
423 int total = 0; \
424 ADDRESS; \
425 S_PRE; \
426 LOOP(BODY); \
427 S_POST; \
428 currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
429 POST_BODY; \
430 WRITEBACK;)
431
432
433#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
434 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
435 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
436 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
437 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
438 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
439 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
450
451// Begin ALU definitions
452
453DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
454 int32_t n = cpu->gprs[rn];
455 cpu->gprs[rd] = n + cpu->shifterOperand;)
456
457DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
458 int32_t n = cpu->gprs[rn];
459 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
460
461DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
462 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
463
464DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
465 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
466
467DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
468 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
469
470DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
471 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
472
473DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
474 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
475
476DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
477 cpu->gprs[rd] = cpu->shifterOperand;)
478
479DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
480 cpu->gprs[rd] = ~cpu->shifterOperand;)
481
482DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
483 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
484
485DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
486 int32_t n = cpu->gprs[rn];
487 cpu->gprs[rd] = cpu->shifterOperand - n;)
488
489DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
490 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
491 cpu->gprs[rd] = cpu->shifterOperand - n;)
492
493DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
494 int32_t n = cpu->gprs[rn];
495 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
496 cpu->gprs[rd] = n - shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
499 int32_t n = cpu->gprs[rn];
500 cpu->gprs[rd] = n - cpu->shifterOperand;)
501
502DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
503 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
504
505DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
506 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
507
508// End ALU definitions
509
510// Begin multiply definitions
511
512DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
513DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
514
515DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
516 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
517 int32_t dm = cpu->gprs[rd];
518 int32_t dn = d;
519 cpu->gprs[rd] = dm + dn;
520 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
521 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
522
523DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
524 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
525 cpu->gprs[rd] = d;
526 cpu->gprs[rdHi] = d >> 32;,
527 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
528
529DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
530 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
531 int32_t dm = cpu->gprs[rd];
532 int32_t dn = d;
533 cpu->gprs[rd] = dm + dn;
534 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
535 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
536
537DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
538 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
539 cpu->gprs[rd] = d;
540 cpu->gprs[rdHi] = d >> 32;,
541 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
542
543// End multiply definitions
544
545// Begin load/store definitions
546
547DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
548DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
549DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
550DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
551DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
552DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
553DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
554DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
555
556DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
557 enum PrivilegeMode priv = cpu->privilegeMode;
558 ARMSetPrivilegeMode(cpu, MODE_USER);
559 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles);
560 ARMSetPrivilegeMode(cpu, priv);
561 ARM_LOAD_POST_BODY;)
562
563DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
564 enum PrivilegeMode priv = cpu->privilegeMode;
565 ARMSetPrivilegeMode(cpu, MODE_USER);
566 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles);
567 ARMSetPrivilegeMode(cpu, priv);
568 ARM_LOAD_POST_BODY;)
569
570DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
571 enum PrivilegeMode priv = cpu->privilegeMode;
572 ARMSetPrivilegeMode(cpu, MODE_USER);
573 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
574 ARMSetPrivilegeMode(cpu, priv);
575 ARM_STORE_POST_BODY;)
576
577DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
578 enum PrivilegeMode priv = cpu->privilegeMode;
579 ARMSetPrivilegeMode(cpu, MODE_USER);
580 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
581 ARMSetPrivilegeMode(cpu, priv);
582 ARM_STORE_POST_BODY;)
583
584DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
585 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr & 0xFFFFFFFC, 0);,
586 ++currentCycles;
587 if (rs & 0x8000) {
588 ARM_WRITE_PC;
589 })
590
591DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
592 cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
593 currentCycles += cpu->memory->activeNonseqCycles32 - cpu->memory->activePrefetchCycles32)
594
595DEFINE_INSTRUCTION_ARM(SWP,
596 int rm = opcode & 0xF;
597 int rd = (opcode >> 12) & 0xF;
598 int rn = (opcode >> 16) & 0xF;
599 int32_t d = cpu->memory->load32(cpu->memory, cpu->gprs[rn], ¤tCycles);
600 cpu->memory->store32(cpu->memory, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
601 cpu->gprs[rd] = d;)
602
603DEFINE_INSTRUCTION_ARM(SWPB,
604 int rm = opcode & 0xF;
605 int rd = (opcode >> 12) & 0xF;
606 int rn = (opcode >> 16) & 0xF;
607 int32_t d = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn], ¤tCycles);
608 cpu->memory->store8(cpu->memory, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
609 cpu->gprs[rd] = d;)
610
611// End load/store definitions
612
613// Begin branch definitions
614
615DEFINE_INSTRUCTION_ARM(B,
616 int32_t offset = opcode << 8;
617 offset >>= 6;
618 cpu->gprs[ARM_PC] += offset;
619 ARM_WRITE_PC;)
620
621DEFINE_INSTRUCTION_ARM(BL,
622 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
623 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
624 cpu->gprs[ARM_PC] += immediate >> 6;
625 ARM_WRITE_PC;)
626
627DEFINE_INSTRUCTION_ARM(BX,
628 int rm = opcode & 0x0000000F;
629 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
630 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
631 if (cpu->executionMode == MODE_THUMB) {
632 THUMB_WRITE_PC;
633 } else {
634 ARM_WRITE_PC;
635 })
636
637// End branch definitions
638
639// Begin coprocessor definitions
640
641DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
642DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
643DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
644DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
645DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
646
647// Begin miscellaneous definitions
648
649DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
650DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
651
652DEFINE_INSTRUCTION_ARM(MSR,
653 int c = opcode & 0x00010000;
654 int f = opcode & 0x00080000;
655 int32_t operand = cpu->gprs[opcode & 0x0000000F];
656 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
657 if (mask & PSR_USER_MASK) {
658 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
659 }
660 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
661 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
662 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
663 }
664 _ARMReadCPSR(cpu);)
665
666DEFINE_INSTRUCTION_ARM(MSRR,
667 int c = opcode & 0x00010000;
668 int f = opcode & 0x00080000;
669 int32_t operand = cpu->gprs[opcode & 0x0000000F];
670 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
671 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
672 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
673
674DEFINE_INSTRUCTION_ARM(MRS, \
675 int rd = (opcode >> 12) & 0xF; \
676 cpu->gprs[rd] = cpu->cpsr.packed;)
677
678DEFINE_INSTRUCTION_ARM(MRSR, \
679 int rd = (opcode >> 12) & 0xF; \
680 cpu->gprs[rd] = cpu->spsr.packed;)
681
682DEFINE_INSTRUCTION_ARM(MSRI,
683 int c = opcode & 0x00010000;
684 int f = opcode & 0x00080000;
685 int rotate = (opcode & 0x00000F00) >> 7;
686 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
687 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
688 if (mask & PSR_USER_MASK) {
689 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
690 }
691 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
692 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
693 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
694 }
695 _ARMReadCPSR(cpu);)
696
697DEFINE_INSTRUCTION_ARM(MSRRI,
698 int c = opcode & 0x00010000;
699 int f = opcode & 0x00080000;
700 int rotate = (opcode & 0x00000F00) >> 7;
701 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
702 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
703 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
704 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
705
706DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
707
708#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
709 EMITTER ## NAME
710
711#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
712 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
713 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
714
715#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
716 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
717 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
718 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
719 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
720 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
721 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
722 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
723 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
724 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
725 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
726 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
727 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
728 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
729 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
730 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
731 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
732
733#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
734 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
735 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
736
737#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
738 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
739 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
740 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
741 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
742 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
743 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
744 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
745 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
746 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
747 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
748 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
749 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
750 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
751 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
752 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
753 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
754
755#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
756 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
757 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
758
759#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
760 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
761
762// TODO: Support coprocessors
763#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
764 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
765 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
766
767#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
768 DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
769
770#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
771 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
772
773#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
774 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
775 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
776 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
777 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
778 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
779 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
780 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
781 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
782 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
783 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
784 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
785 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
786 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
787 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
788 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
789 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
790 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
791 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
792 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
793 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
794 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
795 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
796 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
797 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
798 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
799 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
800 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
801 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
802 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
803 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
804 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
805 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
806 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
807 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
808 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
809 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
822 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
823 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
829 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
831 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
832 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
833 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
834 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
840 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
846 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
847 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
848 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
849 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
850 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
851 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
852 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
853 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
854 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
855 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
856 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
857 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
858 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
859 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
860 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
861 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
862 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
863 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
864 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
865 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
866 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
867 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
868 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
869 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
870 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
871 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
872 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
873 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
874 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
875 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
876 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
877 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
878 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
879 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
880 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
881 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
882 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
883 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
884 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
885 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
886 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
887 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
888 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
889 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
890 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
891 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
892 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
893 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
894 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
895 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
896 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
897 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
898 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
899 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
900 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
901 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
902 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
903 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
904 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
905 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
906 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
907 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
908 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
909 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
910 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
911 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
912 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
913 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
914 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
915 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
916 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
917 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
918 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
919 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
920 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
921 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
922 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
923 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
924 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
925 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
926 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
927 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
928 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
929 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
930 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
931 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
932 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
933 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
934 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
935 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
936 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
937 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
938 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
939 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
940 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
941 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
942 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
943 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
944 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
945 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
946 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
947 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
948 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
949 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
950 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
951 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
952 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
953 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
954 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
955 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
956 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
957 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
958 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
959 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
960 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
961 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
962 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
963 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
964 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
965 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
966 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
967 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
968 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
969 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
970 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
971 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
972 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
973 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
974 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
975 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
976 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
977 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
978 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
979 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
980 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
981 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
982 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
983 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
984 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
985 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
986 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
987 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
988 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
989 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
990 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
991 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
992 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
993 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
994 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
995 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
996 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
997 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
998 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
999 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1000 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1001 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1002 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1003 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1004 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1005 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1006 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1007 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1008 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1009 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1010 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1011 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1012 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1013 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1014 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1015 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1016 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1017 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1018 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1019 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1020 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1021 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1022 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1023 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1024 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1025 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1026 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1027 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1028 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1029 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
1030 DECLARE_ARM_SWI_BLOCK(EMITTER)
1031
1032const ARMInstruction _armTable[0x1000] = {
1033 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1034};