src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18#define SLICE_CYCLES 2048
19
20mLOG_DEFINE_CATEGORY(DS, "DS");
21
22const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
23const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
24const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
25
26static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
27static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
28static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
29
30enum {
31 DS7_SP_BASE = 0x380FD80,
32 DS7_SP_BASE_IRQ = 0x380FF80,
33 DS7_SP_BASE_SVC = 0x380FFC0,
34
35 DS9_SP_BASE = 0x3002F7C,
36 DS9_SP_BASE_IRQ = 0x3003F80,
37 DS9_SP_BASE_SVC = 0x3003FC0,
38};
39
40static void DSInit(void* cpu, struct mCPUComponent* component);
41
42static void DS7Reset(struct ARMCore* cpu);
43static void DS7TestIRQ(struct ARMCore* cpu);
44static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
45static void DS7ProcessEvents(struct ARMCore* cpu);
46
47static void DS9Reset(struct ARMCore* cpu);
48static void DS9TestIRQ(struct ARMCore* cpu);
49static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
50static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
51static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
52static void DS9ProcessEvents(struct ARMCore* cpu);
53
54static void DSProcessEvents(struct DSCommon* dscore);
55static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
56static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
57static void DSBreakpoint(struct ARMCore* cpu, int immediate);
58
59static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
60 UNUSED(cyclesLate);
61 struct DS* ds = context;
62 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
63 if (ds->activeCpu == ds->ds9.cpu) {
64 ds->activeCpu = ds->ds7.cpu;
65 ds->cycleDrift += cycles;
66 cycles = ds->cycleDrift >> 1;
67 timing = &ds->ds7.timing;
68 } else {
69 ds->activeCpu = ds->ds9.cpu;
70 ds->cycleDrift -= cycles << 1;
71 cycles = ds->cycleDrift + SLICE_CYCLES;
72 timing = &ds->ds9.timing;
73 }
74 mTimingSchedule(timing, &ds->slice, cycles);
75 ds->sliceStart = mTimingCurrentTime(timing);
76}
77
78void DSCreate(struct DS* ds) {
79 ds->d.id = DS_COMPONENT_MAGIC;
80 ds->d.init = DSInit;
81 ds->d.deinit = NULL;
82 ds->ds7.p = ds;
83 ds->ds9.p = ds;
84 ds->ds7.cpu = NULL;
85 ds->ds9.cpu = NULL;
86 ds->ds7.ipc = &ds->ds9;
87 ds->ds9.ipc = &ds->ds7;
88}
89
90static void DSInit(void* cpu, struct mCPUComponent* component) {
91 struct DS* ds = (struct DS*) component;
92 struct ARMCore* core = cpu;
93 if (!ds->ds7.cpu) {
94 // The ARM7 must get initialized first
95 ds->ds7.cpu = core;
96 ds->debugger = 0;
97 ds->sync = 0;
98 return;
99 }
100 ds->ds9.cpu = cpu;
101 ds->activeCpu = NULL;
102
103 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
104
105 ds->slice.name = "DS CPU Time Slicing";
106 ds->slice.callback = _slice;
107 ds->slice.context = ds;
108 ds->slice.priority = UINT_MAX;
109
110 CircleBufferInit(&ds->ds7.fifo, 64);
111 CircleBufferInit(&ds->ds9.fifo, 64);
112
113 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
114 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
115 DSMemoryInit(ds);
116 DSDMAInit(ds);
117
118 ds->video.p = ds;
119
120 ds->ds7.springIRQ = 0;
121 ds->ds9.springIRQ = 0;
122 DSTimerInit(ds);
123 ds->keySource = NULL;
124 ds->rtcSource = NULL;
125 ds->rumble = NULL;
126
127 ds->romVf = NULL;
128
129 ds->keyCallback = NULL;
130
131 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
132 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
133}
134
135void DSUnloadROM(struct DS* ds) {
136 if (ds->romVf) {
137 ds->romVf->close(ds->romVf);
138 ds->romVf = NULL;
139 }
140}
141
142void DSDestroy(struct DS* ds) {
143 CircleBufferDeinit(&ds->ds7.fifo);
144 CircleBufferDeinit(&ds->ds9.fifo);
145 DSUnloadROM(ds);
146 DSMemoryDeinit(ds);
147 mTimingDeinit(&ds->ds7.timing);
148 mTimingDeinit(&ds->ds9.timing);
149}
150
151void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
152 irqh->reset = DS7Reset;
153 irqh->processEvents = DS7ProcessEvents;
154 irqh->swi16 = DS7Swi16;
155 irqh->swi32 = DS7Swi32;
156 irqh->hitIllegal = DSIllegal;
157 irqh->readCPSR = DS7TestIRQ;
158 irqh->writeCP15 = NULL;
159 irqh->readCP15 = NULL;
160 irqh->hitStub = DSHitStub;
161 irqh->bkpt16 = DSBreakpoint;
162 irqh->bkpt32 = DSBreakpoint;
163}
164
165void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
166 irqh->reset = DS9Reset;
167 irqh->processEvents = DS9ProcessEvents;
168 irqh->swi16 = NULL;
169 irqh->swi32 = NULL;
170 irqh->hitIllegal = DSIllegal;
171 irqh->readCPSR = DS9TestIRQ;
172 irqh->writeCP15 = DS9WriteCP15;
173 irqh->readCP15 = DS9ReadCP15;
174 irqh->hitStub = DSHitStub;
175 irqh->bkpt16 = DSBreakpoint;
176 irqh->bkpt32 = DSBreakpoint;
177}
178
179void DS7Reset(struct ARMCore* cpu) {
180 ARMSetPrivilegeMode(cpu, MODE_IRQ);
181 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
182 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
183 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
184 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
185 cpu->gprs[ARM_SP] = DS7_SP_BASE;
186
187 struct DS* ds = (struct DS*) cpu->master;
188 mTimingClear(&ds->ds7.timing);
189 CircleBufferInit(&ds->ds7.fifo, 64);
190 DSMemoryReset(ds);
191 DSDMAReset(&ds->ds7);
192 DS7IOInit(ds);
193
194 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
195 if (header) {
196 // TODO: Error check
197 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
198 uint32_t base = header->arm7Base - DS_BASE_RAM;
199 uint32_t* basePointer = &ds->memory.ram[base >> 2];
200 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
201 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
202 }
203 cpu->gprs[12] = header->arm7Entry;
204 cpu->gprs[ARM_LR] = header->arm7Entry;
205 cpu->gprs[ARM_PC] = header->arm7Entry;
206 int currentCycles = 0;
207 ARM_WRITE_PC;
208
209 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
210 }
211}
212
213void DS9Reset(struct ARMCore* cpu) {
214 ARMSetPrivilegeMode(cpu, MODE_IRQ);
215 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
216 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
217 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
218 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
219 cpu->gprs[ARM_SP] = DS9_SP_BASE;
220
221 struct DS* ds = (struct DS*) cpu->master;
222 mTimingClear(&ds->ds9.timing);
223 CircleBufferInit(&ds->ds9.fifo, 64);
224 DSDMAReset(&ds->ds9);
225 DS9IOInit(ds);
226
227 ds->activeCpu = cpu;
228 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
229 ds->cycleDrift = 0;
230 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
231
232 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
233 if (header) {
234 // TODO: Error check
235 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
236 uint32_t base = header->arm9Base - DS_BASE_RAM;
237 uint32_t* basePointer = &ds->memory.ram[base >> 2];
238 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
239 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
240 }
241 cpu->gprs[12] = header->arm9Entry;
242 cpu->gprs[ARM_LR] = header->arm9Entry;
243 cpu->gprs[ARM_PC] = header->arm9Entry;
244 int currentCycles = 0;
245 ARM_WRITE_PC;
246
247 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
248 }
249}
250
251static void DS7ProcessEvents(struct ARMCore* cpu) {
252 struct DS* ds = (struct DS*) cpu->master;
253 DSProcessEvents(&ds->ds7);
254}
255
256static void DS9ProcessEvents(struct ARMCore* cpu) {
257 struct DS* ds = (struct DS*) cpu->master;
258 DSProcessEvents(&ds->ds9);
259}
260
261static void DSProcessEvents(struct DSCommon* dscore) {
262 struct ARMCore* cpu = dscore->cpu;
263 struct DS* ds = dscore->p;
264 if (dscore->springIRQ && !ARMPSRGetI(cpu->cpsr)) {
265 ARMRaiseIRQ(cpu);
266 dscore->springIRQ = 0;
267 }
268
269 int32_t nextEvent = cpu->nextEvent;
270 while (cpu->cycles >= nextEvent) {
271 int32_t cycles = cpu->cycles;
272
273 cpu->cycles = 0;
274 cpu->nextEvent = INT_MAX;
275
276#ifndef NDEBUG
277 if (cycles < 0) {
278 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
279 }
280#endif
281 nextEvent = cycles;
282 do {
283 nextEvent = mTimingTick(&dscore->timing, nextEvent);
284 } while (ds->cpuBlocked);
285
286 cpu->nextEvent = nextEvent;
287
288 if (ds->earlyExit) {
289 ds->earlyExit = false;
290 break;
291 }
292 if (cpu->halted) {
293 cpu->cycles = nextEvent;
294 }
295#ifndef NDEBUG
296 else if (nextEvent < 0) {
297 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
298 }
299#endif
300 }
301}
302
303void DSRunLoop(struct DS* ds) {
304 if (ds->activeCpu == ds->ds9.cpu) {
305 ARMv5RunLoop(ds->ds9.cpu);
306 } else {
307 ARMv4RunLoop(ds->ds7.cpu);
308 }
309}
310
311void DS7Step(struct DS* ds) {
312 while (ds->activeCpu == ds->ds9.cpu) {
313 ARMv5RunLoop(ds->ds9.cpu);
314 }
315 ARMv4Run(ds->ds7.cpu);
316}
317
318void DS9Step(struct DS* ds) {
319 while (ds->activeCpu == ds->ds7.cpu) {
320 ARMv4RunLoop(ds->ds7.cpu);
321 }
322 ARMv5Run(ds->ds9.cpu);
323}
324
325void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
326 ds->debugger = (struct ARMDebugger*) debugger->platform;
327 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
328 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
329 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
330 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
331}
332
333void DSDetachDebugger(struct DS* ds) {
334 ds->debugger = NULL;
335 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
336 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
337 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
338 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
339}
340
341bool DSLoadROM(struct DS* ds, struct VFile* vf) {
342 DSUnloadROM(ds);
343 ds->romVf = vf;
344 // TODO: error check
345 return true;
346}
347
348bool DSIsROM(struct VFile* vf) {
349 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
350 return false;
351 }
352 uint8_t signature[sizeof(DS_ROM_MAGIC)];
353 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
354 return false;
355 }
356 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
357}
358
359bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
360 size_t size = vf->size(vf);
361 void* data = NULL;
362 uint32_t crc;
363 if (size == DS7_SIZE_BIOS) {
364 data = vf->map(vf, size, MAP_READ);
365 } else if (size == 0x1000) {
366 data = vf->map(vf, size, MAP_READ);
367 }
368 if (!data) {
369 return false;
370 }
371 crc = doCrc32(data, size);
372 if (crc == DS7_BIOS_CHECKSUM) {
373 ds->bios7Vf = vf;
374 ds->memory.bios7 = data;
375 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
376 } else if (crc == DS9_BIOS_CHECKSUM) {
377 ds->bios9Vf = vf;
378 ds->memory.bios9 = data;
379 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
380 } else {
381 mLOG(DS, WARN, "BIOS checksum incorrect");
382 vf->unmap(vf, data, size);
383 return false;
384 }
385 return true;
386}
387
388void DSGetGameCode(struct DS* ds, char* out) {
389 memset(out, 0, 8);
390 if (!ds->romVf) {
391 return;
392 }
393
394 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
395 memcpy(out, "NTR-", 4);
396 memcpy(&out[4], &cart->id, 4);
397 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
398}
399
400void DSGetGameTitle(struct DS* ds, char* out) {
401 memset(out, 0, 12);
402 if (!ds->romVf) {
403 return;
404 }
405
406 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
407 memcpy(out, &cart->title, 4);
408 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
409}
410
411void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
412 struct DS* ds = (struct DS*) cpu->master;
413 if (ds->debugger) {
414 struct mDebuggerEntryInfo info = {
415 .address = _ARMPCAddress(cpu),
416 .opcode = opcode
417 };
418 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
419 }
420 // TODO: More sensible category?
421 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
422}
423
424void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
425 struct DS* ds = (struct DS*) cpu->master;
426 if (ds->debugger) {
427 struct mDebuggerEntryInfo info = {
428 .address = _ARMPCAddress(cpu),
429 .opcode = opcode
430 };
431 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
432 } else {
433 ARMRaiseUndefined(cpu);
434 }
435}
436
437void DSBreakpoint(struct ARMCore* cpu, int immediate) {
438 struct DS* ds = (struct DS*) cpu->master;
439 if (immediate >= CPU_COMPONENT_MAX) {
440 return;
441 }
442 switch (immediate) {
443 case CPU_COMPONENT_DEBUGGER:
444 if (ds->debugger) {
445 struct mDebuggerEntryInfo info = {
446 .address = _ARMPCAddress(cpu)
447 };
448 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
449 }
450 break;
451 default:
452 break;
453 }
454}
455
456void DS7TestIRQ(struct ARMCore* cpu) {
457 struct DS* ds = (struct DS*) cpu->master;
458 if (0) {
459 ds->ds7.springIRQ = 1;
460 cpu->nextEvent = cpu->cycles;
461 }
462}
463
464void DS9TestIRQ(struct ARMCore* cpu) {
465 struct DS* ds = (struct DS*) cpu->master;
466 if (0) {
467 ds->ds9.springIRQ = 1;
468 cpu->nextEvent = cpu->cycles;
469 }
470}
471
472static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
473 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
474}
475
476static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
477 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
478 switch (opcode2) {
479 case 0:
480 cpu->cp15.r2.d = value;
481 break;
482 case 1:
483 cpu->cp15.r2.i = value;
484 break;
485 default:
486 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
487 break;
488 }
489}
490
491static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
492 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
493 switch (opcode2) {
494 case 0:
495 cpu->cp15.r3.d = value;
496 break;
497 default:
498 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
499 break;
500 }
501}
502
503static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
504 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
505}
506
507static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
508 cpu->cp15.r6.region[crm] = value;
509 uint32_t base = ARMProtectionGetBase(value) << 12;
510 uint32_t size = 2 << ARMProtectionGetSize(value);
511 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
512}
513
514static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
515 switch (crm) {
516 case 0:
517 if (opcode2 == 4) {
518 ARMHalt(cpu);
519 return;
520 }
521 break;
522 }
523 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
524}
525
526static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
527 uint32_t base = ARMTCMControlGetBase(value) << 12;
528 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
529 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
530 switch (opcode2) {
531 case 0:
532 cpu->cp15.r9.d = value;
533 break;
534 case 1:
535 cpu->cp15.r9.i = value;
536 break;
537 default:
538 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
539 break;
540 }
541}
542
543void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
544 switch (crn) {
545 default:
546 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
547 break;
548 case 0:
549 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
550 ARMRaiseUndefined(cpu);
551 break;
552 case 1:
553 _writeSysControl(cpu, crm, opcode2, value);
554 break;
555 case 2:
556 _writeCacheControl(cpu, crm, opcode2, value);
557 break;
558 case 3:
559 _writeWriteBufferControl(cpu, crm, opcode2, value);
560 break;
561 case 5:
562 _writeAccessControl(cpu, crm, opcode2, value);
563 break;
564 case 6:
565 _writeRegionConfiguration(cpu, crm, opcode2, value);
566 break;
567 case 7:
568 _writeCache(cpu, crm, opcode2, value);
569 break;
570 case 9:
571 _writeTCMControl(cpu, crm, opcode2, value);
572 break;
573 }
574}
575
576static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
577 switch (opcode2) {
578 case 0:
579 return cpu->cp15.r9.d;
580 case 1:
581 return cpu->cp15.r9.i;
582 default:
583 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
584 return 0;
585 }
586}
587
588uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
589 switch (crn) {
590 default:
591 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
592 return 0;
593 case 9:
594 return _readTCMControl(cpu, crm, opcode2);
595 }
596}
597
598void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
599 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
600 ARMRaiseIRQ(cpu);
601 }
602}
603void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
604 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
605 ARMRaiseIRQ(cpu);
606 }
607}
608
609void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
610 if (irq < 16) {
611 io[DS_REG_IF_LO >> 1] |= 1 << irq;
612 } else {
613 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
614 }
615
616 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
617 cpu->halted = 0;
618 if (io[DS_REG_IME >> 1]) {
619 ARMRaiseIRQ(cpu);
620 }
621 }
622}