src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12#define ARM_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles32)
13
14// Addressing mode 1
15static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
16 int rm = opcode & 0x0000000F;
17 int immediate = (opcode & 0x00000F80) >> 7;
18 if (!immediate) {
19 cpu->shifterOperand = cpu->gprs[rm];
20 cpu->shifterCarryOut = cpu->cpsr.c;
21 } else {
22 cpu->shifterOperand = cpu->gprs[rm] << immediate;
23 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
24 }
25}
26
27static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
28 int rm = opcode & 0x0000000F;
29 int rs = (opcode >> 8) & 0x0000000F;
30 ++cpu->cycles;
31 int shift = cpu->gprs[rs];
32 if (rs == ARM_PC) {
33 shift += 4;
34 }
35 shift &= 0xFF;
36 int32_t shiftVal = cpu->gprs[rm];
37 if (rm == ARM_PC) {
38 shiftVal += 4;
39 }
40 if (!shift) {
41 cpu->shifterOperand = shiftVal;
42 cpu->shifterCarryOut = cpu->cpsr.c;
43 } else if (shift < 32) {
44 cpu->shifterOperand = shiftVal << shift;
45 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
46 } else if (shift == 32) {
47 cpu->shifterOperand = 0;
48 cpu->shifterCarryOut = shiftVal & 1;
49 } else {
50 cpu->shifterOperand = 0;
51 cpu->shifterCarryOut = 0;
52 }
53}
54
55static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
56 int rm = opcode & 0x0000000F;
57 int immediate = (opcode & 0x00000F80) >> 7;
58 if (immediate) {
59 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
60 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
61 } else {
62 cpu->shifterOperand = 0;
63 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
64 }
65}
66
67static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
68 int rm = opcode & 0x0000000F;
69 int rs = (opcode >> 8) & 0x0000000F;
70 ++cpu->cycles;
71 int shift = cpu->gprs[rs];
72 if (rs == ARM_PC) {
73 shift += 4;
74 }
75 shift &= 0xFF;
76 uint32_t shiftVal = cpu->gprs[rm];
77 if (rm == ARM_PC) {
78 shiftVal += 4;
79 }
80 if (!shift) {
81 cpu->shifterOperand = shiftVal;
82 cpu->shifterCarryOut = cpu->cpsr.c;
83 } else if (shift < 32) {
84 cpu->shifterOperand = shiftVal >> shift;
85 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
86 } else if (shift == 32) {
87 cpu->shifterOperand = 0;
88 cpu->shifterCarryOut = shiftVal >> 31;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = 0;
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 int immediate = (opcode & 0x00000F80) >> 7;
98 if (immediate) {
99 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
100 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
101 } else {
102 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
103 cpu->shifterOperand = cpu->shifterCarryOut;
104 }
105}
106
107static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
108 int rm = opcode & 0x0000000F;
109 int rs = (opcode >> 8) & 0x0000000F;
110 ++cpu->cycles;
111 int shift = cpu->gprs[rs];
112 if (rs == ARM_PC) {
113 shift += 4;
114 }
115 shift &= 0xFF;
116 int shiftVal = cpu->gprs[rm];
117 if (rm == ARM_PC) {
118 shiftVal += 4;
119 }
120 if (!shift) {
121 cpu->shifterOperand = shiftVal;
122 cpu->shifterCarryOut = cpu->cpsr.c;
123 } else if (shift < 32) {
124 cpu->shifterOperand = shiftVal >> shift;
125 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
126 } else if (cpu->gprs[rm] >> 31) {
127 cpu->shifterOperand = 0xFFFFFFFF;
128 cpu->shifterCarryOut = 1;
129 } else {
130 cpu->shifterOperand = 0;
131 cpu->shifterCarryOut = 0;
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 int immediate = (opcode & 0x00000F80) >> 7;
138 if (immediate) {
139 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
140 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
141 } else {
142 // RRX
143 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
144 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
145 }
146}
147
148static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
149 int rm = opcode & 0x0000000F;
150 int rs = (opcode >> 8) & 0x0000000F;
151 ++cpu->cycles;
152 int shift = cpu->gprs[rs];
153 if (rs == ARM_PC) {
154 shift += 4;
155 }
156 shift &= 0xFF;
157 int shiftVal = cpu->gprs[rm];
158 if (rm == ARM_PC) {
159 shiftVal += 4;
160 }
161 int rotate = shift & 0x1F;
162 if (!shift) {
163 cpu->shifterOperand = shiftVal;
164 cpu->shifterCarryOut = cpu->cpsr.c;
165 } else if (rotate) {
166 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
167 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
168 } else {
169 cpu->shifterOperand = shiftVal;
170 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
171 }
172}
173
174static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
175 int rotate = (opcode & 0x00000F00) >> 7;
176 int immediate = opcode & 0x000000FF;
177 if (!rotate) {
178 cpu->shifterOperand = immediate;
179 cpu->shifterCarryOut = cpu->cpsr.c;
180 } else {
181 cpu->shifterOperand = ARM_ROR(immediate, rotate);
182 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
183 }
184}
185
186static const ARMInstruction _armTable[0x1000];
187
188static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
189 uint32_t opcode;
190 LOAD_32(opcode, address & memory->activeMask, memory->activeRegion);
191 *opcodeOut = opcode;
192 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
193}
194
195void ARMStep(struct ARMCore* cpu) {
196 // TODO
197 uint32_t opcode;
198 cpu->currentPC = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
199 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->currentPC, &opcode);
200 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
201
202 int condition = opcode >> 28;
203 if (condition == 0xE) {
204 instruction(cpu, opcode);
205 return;
206 } else {
207 switch (condition) {
208 case 0x0:
209 if (!ARM_COND_EQ) {
210 cpu->cycles += ARM_PREFETCH_CYCLES;
211 return;
212 }
213 break;
214 case 0x1:
215 if (!ARM_COND_NE) {
216 cpu->cycles += ARM_PREFETCH_CYCLES;
217 return;
218 }
219 break;
220 case 0x2:
221 if (!ARM_COND_CS) {
222 cpu->cycles += ARM_PREFETCH_CYCLES;
223 return;
224 }
225 break;
226 case 0x3:
227 if (!ARM_COND_CC) {
228 cpu->cycles += ARM_PREFETCH_CYCLES;
229 return;
230 }
231 break;
232 case 0x4:
233 if (!ARM_COND_MI) {
234 cpu->cycles += ARM_PREFETCH_CYCLES;
235 return;
236 }
237 break;
238 case 0x5:
239 if (!ARM_COND_PL) {
240 cpu->cycles += ARM_PREFETCH_CYCLES;
241 return;
242 }
243 break;
244 case 0x6:
245 if (!ARM_COND_VS) {
246 cpu->cycles += ARM_PREFETCH_CYCLES;
247 return;
248 }
249 break;
250 case 0x7:
251 if (!ARM_COND_VC) {
252 cpu->cycles += ARM_PREFETCH_CYCLES;
253 return;
254 }
255 break;
256 case 0x8:
257 if (!ARM_COND_HI) {
258 cpu->cycles += ARM_PREFETCH_CYCLES;
259 return;
260 }
261 break;
262 case 0x9:
263 if (!ARM_COND_LS) {
264 cpu->cycles += ARM_PREFETCH_CYCLES;
265 return;
266 }
267 break;
268 case 0xA:
269 if (!ARM_COND_GE) {
270 cpu->cycles += ARM_PREFETCH_CYCLES;
271 return;
272 }
273 break;
274 case 0xB:
275 if (!ARM_COND_LT) {
276 cpu->cycles += ARM_PREFETCH_CYCLES;
277 return;
278 }
279 break;
280 case 0xC:
281 if (!ARM_COND_GT) {
282 cpu->cycles += ARM_PREFETCH_CYCLES;
283 return;
284 }
285 break;
286 case 0xD:
287 if (!ARM_COND_LE) {
288 cpu->cycles += ARM_PREFETCH_CYCLES;
289 return;
290 }
291 break;
292 default:
293 break;
294 }
295 }
296 instruction(cpu, opcode);
297}
298
299// Instruction definitions
300// Beware pre-processor antics
301
302#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
303
304#define ARM_ADDITION_S(M, N, D) \
305 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
306 cpu->cpsr = cpu->spsr; \
307 _ARMReadCPSR(cpu); \
308 } else { \
309 cpu->cpsr.n = ARM_SIGN(D); \
310 cpu->cpsr.z = !(D); \
311 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
312 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
313 }
314
315#define ARM_SUBTRACTION_S(M, N, D) \
316 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
317 cpu->cpsr = cpu->spsr; \
318 _ARMReadCPSR(cpu); \
319 } else { \
320 cpu->cpsr.n = ARM_SIGN(D); \
321 cpu->cpsr.z = !(D); \
322 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
323 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
324 }
325
326#define ARM_NEUTRAL_S(M, N, D) \
327 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
328 cpu->cpsr = cpu->spsr; \
329 _ARMReadCPSR(cpu); \
330 } else { \
331 cpu->cpsr.n = ARM_SIGN(D); \
332 cpu->cpsr.z = !(D); \
333 cpu->cpsr.c = cpu->shifterCarryOut; \
334 }
335
336#define ARM_NEUTRAL_HI_S(DLO, DHI) \
337 cpu->cpsr.n = ARM_SIGN(DHI); \
338 cpu->cpsr.z = !((DHI) | (DLO));
339
340#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
341#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
342#define ADDR_MODE_2_ADDRESS (address)
343#define ADDR_MODE_2_RN (cpu->gprs[rn])
344#define ADDR_MODE_2_RM (cpu->gprs[rm])
345#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
346#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
347#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
348#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
349#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
350#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
351#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
352
353#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
354#define ADDR_MODE_3_RN ADDR_MODE_2_RN
355#define ADDR_MODE_3_RM ADDR_MODE_2_RM
356#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
357#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
358#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
359
360#define ARM_LOAD_POST_BODY \
361 if (rd == ARM_PC) { \
362 ARM_WRITE_PC; \
363 }
364
365#define ARM_STORE_POST_BODY \
366 currentCycles -= ARM_PREFETCH_CYCLES; \
367 currentCycles += 1 + cpu->memory->activeNonseqCycles32;
368
369#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
370 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
371 int currentCycles = ARM_PREFETCH_CYCLES; \
372 BODY; \
373 cpu->cycles += currentCycles; \
374 }
375
376#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
377 DEFINE_INSTRUCTION_ARM(NAME, \
378 int rd = (opcode >> 12) & 0xF; \
379 int rn = (opcode >> 16) & 0xF; \
380 UNUSED(rn); \
381 SHIFTER(cpu, opcode); \
382 BODY; \
383 S_BODY; \
384 if (rd == ARM_PC) { \
385 if (cpu->executionMode == MODE_ARM) { \
386 ARM_WRITE_PC; \
387 } else { \
388 THUMB_WRITE_PC; \
389 } \
390 })
391
392#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
393 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
394 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
395 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
396 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
397 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
398 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
399 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
400 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
401 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
402 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
403 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
404 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
405 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
406 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
407 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
408 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
409 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
410 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
411
412#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
413 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
414 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
415 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
416 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
417 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
418 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
419 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
420 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
421 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
422
423#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
424 DEFINE_INSTRUCTION_ARM(NAME, \
425 int rd = (opcode >> 12) & 0xF; \
426 int rdHi = (opcode >> 16) & 0xF; \
427 int rs = (opcode >> 8) & 0xF; \
428 int rm = opcode & 0xF; \
429 UNUSED(rdHi); \
430 ARM_WAIT_MUL(cpu->gprs[rs]); \
431 BODY; \
432 S_BODY; \
433 if (rd == ARM_PC) { \
434 ARM_WRITE_PC; \
435 })
436
437#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
438 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
439 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
440
441#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
442 DEFINE_INSTRUCTION_ARM(NAME, \
443 uint32_t address; \
444 int rn = (opcode >> 16) & 0xF; \
445 int rd = (opcode >> 12) & 0xF; \
446 int rm = opcode & 0xF; \
447 UNUSED(rm); \
448 address = ADDRESS; \
449 WRITEBACK; \
450 BODY;)
451
452#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
459
460#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
471
472#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
473 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
474 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
478 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
479 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
480 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
481 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
482 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
483 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
485
486#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
487 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
488 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
489
490#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
491 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
492 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
493 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
494 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
495 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
496 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
497
498#define ARM_MS_PRE \
499 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
500 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
501
502#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
503
504#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
505#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
506#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
507#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
508#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
509#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
510#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
511#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
512
513#define ARM_M_INCREMENT(BODY) \
514 for (m = rs, i = 0; m; m >>= 1, ++i) { \
515 if (m & 1) { \
516 BODY; \
517 addr += 4; \
518 total += 1; \
519 } \
520 }
521
522#define ARM_M_DECREMENT(BODY) \
523 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
524 if (rs & m) { \
525 BODY; \
526 addr -= 4; \
527 total += 1; \
528 } \
529 }
530
531#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
532 DEFINE_INSTRUCTION_ARM(NAME, \
533 int rn = (opcode >> 16) & 0xF; \
534 int rs = opcode & 0x0000FFFF; \
535 int m; \
536 int i; \
537 int total = 0; \
538 ADDRESS; \
539 S_PRE; \
540 LOOP(BODY); \
541 S_POST; \
542 currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
543 POST_BODY; \
544 WRITEBACK;)
545
546
547#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
548 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
549 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
550 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
551 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
552 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
553 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
554 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
555 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
556 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
557 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
558 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
559 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
560 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
561 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
562 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
563 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
564
565// Begin ALU definitions
566
567DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
568 int32_t n = cpu->gprs[rn];
569 cpu->gprs[rd] = n + cpu->shifterOperand;)
570
571DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
572 int32_t n = cpu->gprs[rn];
573 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
574
575DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
576 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
577
578DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
579 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
580
581DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
582 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
583
584DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
585 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
586
587DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
588 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
589
590DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
591 cpu->gprs[rd] = cpu->shifterOperand;)
592
593DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
594 cpu->gprs[rd] = ~cpu->shifterOperand;)
595
596DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
597 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
598
599DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
600 int32_t n = cpu->gprs[rn];
601 cpu->gprs[rd] = cpu->shifterOperand - n;)
602
603DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
604 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
605 cpu->gprs[rd] = cpu->shifterOperand - n;)
606
607DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
608 int32_t n = cpu->gprs[rn];
609 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
610 cpu->gprs[rd] = n - shifterOperand;)
611
612DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
613 int32_t n = cpu->gprs[rn];
614 cpu->gprs[rd] = n - cpu->shifterOperand;)
615
616DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
617 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
618
619DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
620 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
621
622// End ALU definitions
623
624// Begin multiply definitions
625
626DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
627DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
628
629DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
630 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
631 int32_t dm = cpu->gprs[rd];
632 int32_t dn = d;
633 cpu->gprs[rd] = dm + dn;
634 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
635 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
636
637DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
638 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
639 cpu->gprs[rd] = d;
640 cpu->gprs[rdHi] = d >> 32;,
641 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
642
643DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
644 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
645 int32_t dm = cpu->gprs[rd];
646 int32_t dn = d;
647 cpu->gprs[rd] = dm + dn;
648 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
649 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
650
651DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
652 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
653 cpu->gprs[rd] = d;
654 cpu->gprs[rdHi] = d >> 32;,
655 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
656
657// End multiply definitions
658
659// Begin load/store definitions
660
661DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
662DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
663DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
664DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
665DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
666DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
667DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
668DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
669
670DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
671 enum PrivilegeMode priv = cpu->privilegeMode;
672 ARMSetPrivilegeMode(cpu, MODE_USER);
673 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles);
674 ARMSetPrivilegeMode(cpu, priv);
675 ARM_LOAD_POST_BODY;)
676
677DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
678 enum PrivilegeMode priv = cpu->privilegeMode;
679 ARMSetPrivilegeMode(cpu, MODE_USER);
680 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles);
681 ARMSetPrivilegeMode(cpu, priv);
682 ARM_LOAD_POST_BODY;)
683
684DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
685 enum PrivilegeMode priv = cpu->privilegeMode;
686 ARMSetPrivilegeMode(cpu, MODE_USER);
687 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
688 ARMSetPrivilegeMode(cpu, priv);
689 ARM_STORE_POST_BODY;)
690
691DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
692 enum PrivilegeMode priv = cpu->privilegeMode;
693 ARMSetPrivilegeMode(cpu, MODE_USER);
694 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
695 ARMSetPrivilegeMode(cpu, priv);
696 ARM_STORE_POST_BODY;)
697
698DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
699 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr & 0xFFFFFFFC, 0);,
700 ++currentCycles;
701 if (rs & 0x8000) {
702 ARM_WRITE_PC;
703 })
704
705DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
706 cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
707 currentCycles += cpu->memory->activeNonseqCycles32 - cpu->memory->activePrefetchCycles32)
708
709DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
710DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
711
712// End load/store definitions
713
714// Begin branch definitions
715
716DEFINE_INSTRUCTION_ARM(B,
717 int32_t offset = opcode << 8;
718 offset >>= 6;
719 cpu->gprs[ARM_PC] += offset;
720 ARM_WRITE_PC;)
721
722DEFINE_INSTRUCTION_ARM(BL,
723 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
724 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
725 cpu->gprs[ARM_PC] += immediate >> 6;
726 ARM_WRITE_PC;)
727
728DEFINE_INSTRUCTION_ARM(BX,
729 int rm = opcode & 0x0000000F;
730 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
731 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
732 if (cpu->executionMode == MODE_THUMB) {
733 THUMB_WRITE_PC;
734 } else {
735 ARM_WRITE_PC;
736 })
737
738// End branch definitions
739
740// Begin coprocessor definitions
741
742DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
743DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
744DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
745DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
746DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
747
748// Begin miscellaneous definitions
749
750DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
751DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
752
753DEFINE_INSTRUCTION_ARM(MSR,
754 int c = opcode & 0x00010000;
755 int f = opcode & 0x00080000;
756 int32_t operand = cpu->gprs[opcode & 0x0000000F];
757 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
758 if (mask & PSR_USER_MASK) {
759 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
760 }
761 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
762 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
763 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
764 })
765
766DEFINE_INSTRUCTION_ARM(MSRR,
767 int c = opcode & 0x00010000;
768 int f = opcode & 0x00080000;
769 int32_t operand = cpu->gprs[opcode & 0x0000000F];
770 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
771 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
772 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
773
774DEFINE_INSTRUCTION_ARM(MRS, \
775 int rd = (opcode >> 12) & 0xF; \
776 cpu->gprs[rd] = cpu->cpsr.packed;)
777
778DEFINE_INSTRUCTION_ARM(MRSR, \
779 int rd = (opcode >> 12) & 0xF; \
780 cpu->gprs[rd] = cpu->spsr.packed;)
781
782DEFINE_INSTRUCTION_ARM(MSRI,
783 int c = opcode & 0x00010000;
784 int f = opcode & 0x00080000;
785 int rotate = (opcode & 0x00000F00) >> 8;
786 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
787 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
788 if (mask & PSR_USER_MASK) {
789 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
790 }
791 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
792 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
793 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
794 })
795
796DEFINE_INSTRUCTION_ARM(MSRRI,
797 int c = opcode & 0x00010000;
798 int f = opcode & 0x00080000;
799 int rotate = (opcode & 0x00000F00) >> 8;
800 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
801 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
802 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
803 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
804
805DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
806
807#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
808 EMITTER ## NAME
809
810#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
811 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
812 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
813
814#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
822 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
823 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
829 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
831
832#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
833 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
834 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
835
836#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
837 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
846 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
847 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
848 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
849 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
850 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
851 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
852 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
853
854#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
855 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
856 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
857
858#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
859 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
860
861// TODO: Support coprocessors
862#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
863 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
864 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
865
866#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
867 DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
868
869#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
870 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
871
872#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
873 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
874 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
875 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
876 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
877 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
878 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
879 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
880 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
881 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
882 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
883 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
884 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
885 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
886 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
887 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
888 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
889 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
890 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
891 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
892 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
893 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
894 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
895 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
896 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
897 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
898 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
899 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
900 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
901 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
902 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
903 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
904 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
905 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
906 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
907 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
908 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
909 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
910 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
911 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
912 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
913 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
914 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
915 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
916 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
917 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
918 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
919 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
920 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
921 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
922 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
923 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
924 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
925 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
926 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
927 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
928 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
929 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
930 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
931 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
932 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
933 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
934 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
935 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
936 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
937 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
938 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
939 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
940 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
941 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
942 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
943 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
944 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
945 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
946 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
947 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
948 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
949 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
950 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
951 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
952 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
953 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
954 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
955 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
956 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
957 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
958 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
959 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
960 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
961 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
962 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
963 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
964 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
965 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
966 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
967 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
968 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
969 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
970 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
971 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
972 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
973 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
974 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
975 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
976 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
977 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
978 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
979 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
980 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
981 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
982 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
983 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
984 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
985 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
986 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
987 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
988 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
989 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
990 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
991 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
992 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
993 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
994 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
995 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
996 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
997 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
998 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
999 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
1000 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
1001 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
1002 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
1003 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
1004 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
1005 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
1006 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
1007 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
1008 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
1009 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
1010 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
1011 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
1012 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
1013 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
1014 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
1015 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
1016 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
1017 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
1018 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
1019 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
1020 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
1021 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
1022 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
1023 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
1024 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
1025 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
1026 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
1027 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
1028 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
1029 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
1030 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
1031 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
1032 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
1033 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
1034 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
1035 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
1036 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
1037 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
1038 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
1039 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
1040 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
1041 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
1042 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
1043 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
1044 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
1045 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
1046 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
1047 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
1048 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
1049 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
1050 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
1051 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
1052 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
1053 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
1054 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
1055 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
1056 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
1057 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
1058 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
1059 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
1060 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
1061 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
1062 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
1063 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
1064 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
1065 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
1066 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
1067 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
1068 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
1069 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
1070 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
1071 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
1072 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
1073 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
1074 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
1075 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
1076 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
1077 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
1078 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
1079 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
1080 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
1081 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
1082 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
1083 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
1084 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
1085 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
1086 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
1087 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
1088 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
1089 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
1090 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
1091 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
1092 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
1093 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
1094 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
1095 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
1096 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
1097 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
1098 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1099 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1100 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1101 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1102 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1103 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1104 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1105 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1106 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1107 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1108 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1109 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1110 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1111 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1112 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1113 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1114 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1115 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1116 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1117 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1118 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1119 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1120 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1121 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1122 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1123 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1124 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1125 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1126 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1127 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1128 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
1129 DECLARE_ARM_SWI_BLOCK(EMITTER)
1130
1131static const ARMInstruction _armTable[0x1000] = {
1132 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1133};