1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_CART_HALFBANK1 = 0x4000,
 26	GB_BASE_CART_HALFBANK2 = 0x6000,
 27	GB_BASE_VRAM = 0x8000,
 28	GB_BASE_EXTERNAL_RAM = 0xA000,
 29	GB_BASE_EXTERNAL_RAM_HALFBANK0 = 0xA000,
 30	GB_BASE_EXTERNAL_RAM_HALFBANK1 = 0xB000,
 31	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 32	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 33	GB_BASE_OAM = 0xFE00,
 34	GB_BASE_UNUSABLE = 0xFEA0,
 35	GB_BASE_IO = 0xFF00,
 36	GB_BASE_HRAM = 0xFF80,
 37	GB_BASE_IE = 0xFFFF
 38};
 39
 40enum {
 41	GB_REGION_CART_BANK0 = 0x0,
 42	GB_REGION_CART_BANK1 = 0x4,
 43	GB_REGION_VRAM = 0x8,
 44	GB_REGION_EXTERNAL_RAM = 0xA,
 45	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 46	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 47	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 48	GB_REGION_OTHER = 0xF,
 49};
 50
 51enum {
 52	GB_SIZE_CART_BANK0 = 0x4000,
 53	GB_SIZE_CART_HALFBANK = 0x2000,
 54	GB_SIZE_CART_MAX = 0x800000,
 55	GB_SIZE_VRAM = 0x4000,
 56	GB_SIZE_VRAM_BANK0 = 0x2000,
 57	GB_SIZE_EXTERNAL_RAM = 0x2000,
 58	GB_SIZE_EXTERNAL_RAM_HALFBANK = 0x1000,
 59	GB_SIZE_WORKING_RAM = 0x8000,
 60	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 61	GB_SIZE_OAM = 0xA0,
 62	GB_SIZE_IO = 0x80,
 63	GB_SIZE_HRAM = 0x7F,
 64};
 65
 66enum {
 67	GB_SRAM_DIRT_NEW = 1,
 68	GB_SRAM_DIRT_SEEN = 2
 69};
 70
 71struct GBMemory;
 72typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
 73typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
 74
 75DECL_BITFIELD(GBMBC7Field, uint8_t);
 76DECL_BIT(GBMBC7Field, CS, 7);
 77DECL_BIT(GBMBC7Field, CLK, 6);
 78DECL_BIT(GBMBC7Field, DI, 1);
 79DECL_BIT(GBMBC7Field, DO, 0);
 80
 81enum GBMBC7MachineState {
 82	GBMBC7_STATE_IDLE = 0,
 83	GBMBC7_STATE_READ_COMMAND = 1,
 84	GBMBC7_STATE_DO = 2,
 85
 86	GBMBC7_STATE_EEPROM_EWDS = 0x10,
 87	GBMBC7_STATE_EEPROM_WRAL = 0x11,
 88	GBMBC7_STATE_EEPROM_ERAL = 0x12,
 89	GBMBC7_STATE_EEPROM_EWEN = 0x13,
 90	GBMBC7_STATE_EEPROM_WRITE = 0x14,
 91	GBMBC7_STATE_EEPROM_READ = 0x18,
 92	GBMBC7_STATE_EEPROM_ERASE = 0x1C,
 93};
 94
 95enum GBTAMA5Register {
 96	GBTAMA5_BANK_LO = 0x0,
 97	GBTAMA5_BANK_HI = 0x1,
 98	GBTAMA5_WRITE_LO = 0x4,
 99	GBTAMA5_WRITE_HI = 0x5,
100	GBTAMA5_CS = 0x6,
101	GBTAMA5_ADDR_LO = 0x7,
102	GBTAMA5_MAX = 0x8,
103	GBTAMA5_ACTIVE = 0xA,
104	GBTAMA5_READ_LO = 0xC,
105	GBTAMA5_READ_HI = 0xD,
106};
107
108struct GBMBC1State {
109	int mode;
110	int multicartStride;
111};
112
113struct GBMBC6State {
114	int currentBank1;
115	uint8_t* romBank1;
116	bool sramAccess;
117	int currentSramBank1;
118	uint8_t* sramBank1;
119};
120
121struct GBMBC7State {
122	enum GBMBC7MachineState state;
123	uint16_t sr;
124	uint8_t address;
125	bool writable;
126	int srBits;
127	uint8_t access;
128	uint8_t latch;
129	GBMBC7Field eeprom;
130};
131
132struct GBMMM01State {
133	bool locked;
134	int currentBank0;
135};
136
137struct GBPocketCamState {
138	bool registersActive;
139	uint8_t registers[0x36];
140};
141
142struct GBTAMA5State {
143	uint8_t reg;
144	uint8_t registers[GBTAMA5_MAX];
145};
146
147union GBMBCState {
148	struct GBMBC1State mbc1;
149	struct GBMBC6State mbc6;
150	struct GBMBC7State mbc7;
151	struct GBMMM01State mmm01;
152	struct GBPocketCamState pocketCam;
153	struct GBTAMA5State tama5;
154};
155
156struct mRotationSource;
157struct GBMemory {
158	uint8_t* rom;
159	uint8_t* romBase;
160	uint8_t* romBank;
161	enum GBMemoryBankControllerType mbcType;
162	GBMemoryBankControllerWrite mbcWrite;
163	GBMemoryBankControllerRead mbcRead;
164	union GBMBCState mbcState;
165	int currentBank;
166
167	uint8_t* wram;
168	uint8_t* wramBank;
169	int wramCurrentBank;
170
171	bool sramAccess;
172	uint8_t* sram;
173	uint8_t* sramBank;
174	int sramCurrentBank;
175
176	uint8_t io[GB_SIZE_IO];
177	bool ime;
178	uint8_t ie;
179
180	uint8_t hram[GB_SIZE_HRAM];
181
182	uint16_t dmaSource;
183	uint16_t dmaDest;
184	int dmaRemaining;
185
186	uint16_t hdmaSource;
187	uint16_t hdmaDest;
188	int hdmaRemaining;
189	bool isHdma;
190
191	struct mTimingEvent dmaEvent;
192	struct mTimingEvent hdmaEvent;
193
194	size_t romSize;
195
196	bool rtcAccess;
197	int activeRtcReg;
198	bool rtcLatched;
199	uint8_t rtcRegs[5];
200	time_t rtcLastLatch;
201	struct mRTCSource* rtc;
202	struct mRotationSource* rotation;
203	struct mRumble* rumble;
204	struct mImageSource* cam;
205};
206
207struct LR35902Core;
208void GBMemoryInit(struct GB* gb);
209void GBMemoryDeinit(struct GB* gb);
210
211void GBMemoryReset(struct GB* gb);
212void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
213
214uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
215void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
216
217int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
218
219uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
220
221void GBMemoryDMA(struct GB* gb, uint16_t base);
222uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
223
224void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
225
226struct GBSerializedState;
227void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
228void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
229
230CXX_GUARD_END
231
232#endif