GB: Fix IRQ disabling on the same T-cycle as an assert
Vicki Pfau vi@endrift.com
Thu, 09 Aug 2018 19:11:26 -0700
4 files changed,
9 insertions(+),
6 deletions(-)
M
CHANGES
→
CHANGES
@@ -45,6 +45,7 @@ - GB Video: Fix SCX timing
- GBA Video: Improve sprite cycle counting (fixes mgba.io/i/1126) - GB, GBA Savedata: Fix savestate loading overwriting saves on reset - GBA Video: Make layer disabling work consistently + - GB: Fix IRQ disabling on the same T-cycle as an assert Misc: - GBA Timer: Use global cycles for timers - GBA: Extend oddly-sized ROMs to full address space (fixes mgba.io/i/722)
M
src/gb/gb.c
→
src/gb/gb.c
@@ -625,7 +625,11 @@ return;
} gb->cpu->halted = false; - if (!gb->memory.ime || gb->cpu->irqPending) { + if (!gb->memory.ime) { + gb->cpu->irqPending = false; + return; + } + if (gb->cpu->irqPending) { return; } LR35902RaiseIRQ(gb->cpu);@@ -661,12 +665,11 @@ }
void GBSetInterrupts(struct LR35902Core* cpu, bool enable) { struct GB* gb = (struct GB*) cpu->master; + mTimingDeschedule(&gb->timing, &gb->eiPending); if (!enable) { - gb->memory.ime = enable; - mTimingDeschedule(&gb->timing, &gb->eiPending); + gb->memory.ime = false; GBUpdateIRQs(gb); } else { - mTimingDeschedule(&gb->timing, &gb->eiPending); mTimingSchedule(&gb->timing, &gb->eiPending, 4); } }
M
src/lr35902/lr35902.c
→
src/lr35902/lr35902.c
@@ -137,7 +137,7 @@ }
} void LR35902Tick(struct LR35902Core* cpu) { - if (cpu->cycles >= cpu->nextEvent) { + while (cpu->cycles >= cpu->nextEvent) { cpu->irqh.processEvents(cpu); } _LR35902Step(cpu);