Ensure LDM does not write back incorrectly with register list overlaps
Jeffrey Pfau jeffrey@endrift.com
Sat, 27 Jul 2013 03:02:52 -0700
1 files changed,
9 insertions(+),
2 deletions(-)
jump to
M
src/arm/isa-arm.c
→
src/arm/isa-arm.c
@@ -530,6 +530,7 @@ #define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
DEFINE_INSTRUCTION_ARM(NAME, \ int rn = (opcode >> 16) & 0xF; \ int rs = opcode & 0x0000FFFF; \ + int writeback = 1; \ int m; \ int i; \ int total = 0; \@@ -537,9 +538,11 @@ ADDRESS; \
S_PRE; \ LOOP(BODY); \ S_POST; \ - WRITEBACK; \ currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \ - POST_BODY;) + POST_BODY; \ + if (writeback) { \ + WRITEBACK; \ + }) #define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \@@ -699,6 +702,10 @@ cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr, 0);,
++currentCycles; if (rs & 0x8000) { ARM_WRITE_PC; + } + int rnx = 1 << rn; + if (rnx & rs && ((rnx - 1) & rs)) { + writeback = 0; }) DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,