git rekt — mgba.git: 4fbed66bdb1cb69f60c6fa4642c778e6cc071fe3

Start fleshing out addressing mode 1

Jeffrey Pfau jeffrey@endrift.com

Thu, 11 Apr 2013 01:32:30 -0700

commit

4fbed66bdb1cb69f60c6fa4642c778e6cc071fe3

parent

d278429b43a1a42f4320da13ae9e044007f942e0

1 files changed, 140 insertions(+), 14 deletions(-)

jump to

src/isa-arm.c

M src/isa-arm.c → src/isa-arm.c

@@ -10,8 +10,61 @@ PSR_STATE_MASK = 0x00000020
 };
 
 // Addressing mode 1
-static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
-	// TODO
+static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+	int immediate = (opcode & 0x00000F80) >> 7;
+	if (!immediate) {
+		cpu->shifterOperand = cpu->gprs[rm];
+		cpu->shifterCarryOut = cpu->cpsr.c;
+	} else {
+		cpu->shifterOperand = cpu->gprs[rm] << immediate;
+		cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
+	}
+}
+
+static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+}
+
+static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+	int immediate = (opcode & 0x00000F80) >> 7;
+	if (immediate) {
+		cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
+		cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
+	} else {
+		cpu->shifterOperand = 0;
+		cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
+	}
+}
+
+static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+}
+
+static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+	int immediate = (opcode & 0x00000F80) >> 7;
+	if (immediate) {
+		cpu->shifterOperand = cpu->gprs[rm] >> immediate;
+		cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
+	} else {
+		cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
+		cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
+	}
+}
+
+static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+}
+
+static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
+	int immediate = (opcode & 0x00000F80) >> 7;
+}
+
+static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
+	int rm = opcode & 0x0000000F;
 }
 
 static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
@@ -195,14 +248,35 @@ ARM_WRITE_PC; \
 		})
 
 #define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
 
 #define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, _barrelShift, BODY, POST_BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
+	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
 
 #define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
 	DEFINE_INSTRUCTION_ARM(NAME, \
@@ -467,14 +541,21 @@ DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
 	DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
 
 #define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
-	DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
 
 #define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
@@ -535,7 +616,22 @@ DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
-	DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
@@ -554,9 +650,39 @@ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
-	DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
-	DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
 	DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \

all repos — mgba @ 4fbed66bdb1cb69f60c6fa4642c778e6cc071fe3

mGBA Game Boy Advance Emulator