M CHANGES → CHANGES

@@ -10,6 +10,7 @@ - Qt: Window size command line options are now supported
  - Qt: Increase usability of key mapper
  - GBA Memory: Use a dynamically sized mask for ROM memory
  - Qt: Remove useless help icons in dialogs
+ - ARM7: Combine shifter-immediate and shifter-register functions to reduce binary size
 
 0.3.0: (2015-08-16)
 Features:

M src/arm/decoder-arm.c → src/arm/decoder-arm.c

@@ -11,18 +11,16 @@ #include "isa-inlines.h"
 
 #define ADDR_MODE_1_SHIFT(OP) \
 	info->op3.reg = opcode & 0x0000000F; \
-	info->op3.shifterOp = ARM_SHIFT_ ## OP; \
-	info->op3.shifterImm = (opcode >> 7) & 0x1F; \
-	info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
-		ARM_OPERAND_SHIFT_IMMEDIATE_3;
-
-#define ADDR_MODE_1_SHIFTR(OP) \
-	info->op3.reg = opcode & 0x0000000F; \
-	info->op3.shifterOp = ARM_SHIFT_ ## OP; \
-	info->op3.shifterReg = (opcode >> 8) & 0xF; \
-	++info->iCycles; \
-	info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
-		ARM_OPERAND_SHIFT_REGISTER_3;
+	info->operandFormat |= ARM_OPERAND_REGISTER_3; \
+	if (opcode & 0x00000010) { \
+		info->op3.shifterOp = ARM_SHIFT_ ## OP; \
+		info->op3.shifterReg = (opcode >> 8) & 0xF; \
+		++info->iCycles; \
+		info->operandFormat |= ARM_OPERAND_SHIFT_REGISTER_3; \
+	} else { \
+		info->op3.shifterImm = (opcode >> 7) & 0x1F; \
+		info->operandFormat |= ARM_OPERAND_SHIFT_IMMEDIATE_3; \
+	}
 
 #define ADDR_MODE_1_LSL \
 	ADDR_MODE_1_SHIFT(LSL) \
@@ -38,11 +36,6 @@ ADDR_MODE_1_SHIFT(ROR) \
 	if (!info->op3.shifterImm) { \
 		info->op3.shifterOp = ARM_SHIFT_RRX; \
 	}
-
-#define ADDR_MODE_1_LSLR ADDR_MODE_1_SHIFTR(LSL)
-#define ADDR_MODE_1_LSRR ADDR_MODE_1_SHIFTR(LSR)
-#define ADDR_MODE_1_ASRR ADDR_MODE_1_SHIFTR(ASR)
-#define ADDR_MODE_1_RORR ADDR_MODE_1_SHIFTR(ROR)
 
 #define ADDR_MODE_1_IMM \
 	int rotate = (opcode & 0x00000F00) >> 7; \
@@ -121,32 +114,20 @@
 #define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 0, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 0, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 0, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 0, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## S_RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
 
 #define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_NONE, 1) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_NONE, 1) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_NONE, 1) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
-	DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_NONE, 1) \
 	DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
 
 #define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \

M src/arm/emitter-arm.h → src/arm/emitter-arm.h

@@ -17,13 +17,13 @@ DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
 
 #define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
-	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
+	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
 	DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \

M src/arm/isa-arm.c → src/arm/isa-arm.c

@@ -16,160 +16,156 @@
 // Addressing mode 1
 static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;
-	int immediate = (opcode & 0x00000F80) >> 7;
-	if (!immediate) {
-		cpu->shifterOperand = cpu->gprs[rm];
-		cpu->shifterCarryOut = cpu->cpsr.c;
-	} else {
-		cpu->shifterOperand = cpu->gprs[rm] << immediate;
-		cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
-	}
-}
-
-static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
-	int rm = opcode & 0x0000000F;
-	int rs = (opcode >> 8) & 0x0000000F;
-	++cpu->cycles;
-	int shift = cpu->gprs[rs];
-	if (rs == ARM_PC) {
-		shift += 4;
-	}
-	shift &= 0xFF;
-	int32_t shiftVal = cpu->gprs[rm];
-	if (rm == ARM_PC) {
-		shiftVal += 4;
-	}
-	if (!shift) {
-		cpu->shifterOperand = shiftVal;
-		cpu->shifterCarryOut = cpu->cpsr.c;
-	} else if (shift < 32) {
-		cpu->shifterOperand = shiftVal << shift;
-		cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
-	} else if (shift == 32) {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = shiftVal & 1;
+	if (opcode & 0x00000010) {
+		int rs = (opcode >> 8) & 0x0000000F;
+		++cpu->cycles;
+		int shift = cpu->gprs[rs];
+		if (rs == ARM_PC) {
+			shift += 4;
+		}
+		shift &= 0xFF;
+		int32_t shiftVal = cpu->gprs[rm];
+		if (rm == ARM_PC) {
+			shiftVal += 4;
+		}
+		if (!shift) {
+			cpu->shifterOperand = shiftVal;
+			cpu->shifterCarryOut = cpu->cpsr.c;
+		} else if (shift < 32) {
+			cpu->shifterOperand = shiftVal << shift;
+			cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
+		} else if (shift == 32) {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = shiftVal & 1;
+		} else {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = 0;
+		}
 	} else {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = 0;
+		int immediate = (opcode & 0x00000F80) >> 7;
+		if (!immediate) {
+			cpu->shifterOperand = cpu->gprs[rm];
+			cpu->shifterCarryOut = cpu->cpsr.c;
+		} else {
+			cpu->shifterOperand = cpu->gprs[rm] << immediate;
+			cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
+		}
 	}
 }
 
 static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;
-	int immediate = (opcode & 0x00000F80) >> 7;
-	if (immediate) {
-		cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
-		cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
+	if (opcode & 0x00000010) {
+		int rs = (opcode >> 8) & 0x0000000F;
+		++cpu->cycles;
+		int shift = cpu->gprs[rs];
+		if (rs == ARM_PC) {
+			shift += 4;
+		}
+		shift &= 0xFF;
+		uint32_t shiftVal = cpu->gprs[rm];
+		if (rm == ARM_PC) {
+			shiftVal += 4;
+		}
+		if (!shift) {
+			cpu->shifterOperand = shiftVal;
+			cpu->shifterCarryOut = cpu->cpsr.c;
+		} else if (shift < 32) {
+			cpu->shifterOperand = shiftVal >> shift;
+			cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
+		} else if (shift == 32) {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = shiftVal >> 31;
+		} else {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = 0;
+		}
 	} else {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
-	}
-}
-
-static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
-	int rm = opcode & 0x0000000F;
-	int rs = (opcode >> 8) & 0x0000000F;
-	++cpu->cycles;
-	int shift = cpu->gprs[rs];
-	if (rs == ARM_PC) {
-		shift += 4;
-	}
-	shift &= 0xFF;
-	uint32_t shiftVal = cpu->gprs[rm];
-	if (rm == ARM_PC) {
-		shiftVal += 4;
-	}
-	if (!shift) {
-		cpu->shifterOperand = shiftVal;
-		cpu->shifterCarryOut = cpu->cpsr.c;
-	} else if (shift < 32) {
-		cpu->shifterOperand = shiftVal >> shift;
-		cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
-	} else if (shift == 32) {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = shiftVal >> 31;
-	} else {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = 0;
+		int immediate = (opcode & 0x00000F80) >> 7;
+		if (immediate) {
+			cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
+			cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
+		} else {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
+		}
 	}
 }
 
 static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;
-	int immediate = (opcode & 0x00000F80) >> 7;
-	if (immediate) {
-		cpu->shifterOperand = cpu->gprs[rm] >> immediate;
-		cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
-	} else {
-		cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
-		cpu->shifterOperand = cpu->shifterCarryOut;
-	}
-}
-
-static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
-	int rm = opcode & 0x0000000F;
-	int rs = (opcode >> 8) & 0x0000000F;
-	++cpu->cycles;
-	int shift = cpu->gprs[rs];
-	if (rs == ARM_PC) {
-		shift += 4;
-	}
-	shift &= 0xFF;
-	int shiftVal =  cpu->gprs[rm];
-	if (rm == ARM_PC) {
-		shiftVal += 4;
-	}
-	if (!shift) {
-		cpu->shifterOperand = shiftVal;
-		cpu->shifterCarryOut = cpu->cpsr.c;
-	} else if (shift < 32) {
-		cpu->shifterOperand = shiftVal >> shift;
-		cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
-	} else if (cpu->gprs[rm] >> 31) {
-		cpu->shifterOperand = 0xFFFFFFFF;
-		cpu->shifterCarryOut = 1;
+	if (opcode & 0x00000010) {
+		int rs = (opcode >> 8) & 0x0000000F;
+		++cpu->cycles;
+		int shift = cpu->gprs[rs];
+		if (rs == ARM_PC) {
+			shift += 4;
+		}
+		shift &= 0xFF;
+		int shiftVal =  cpu->gprs[rm];
+		if (rm == ARM_PC) {
+			shiftVal += 4;
+		}
+		if (!shift) {
+			cpu->shifterOperand = shiftVal;
+			cpu->shifterCarryOut = cpu->cpsr.c;
+		} else if (shift < 32) {
+			cpu->shifterOperand = shiftVal >> shift;
+			cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
+		} else if (cpu->gprs[rm] >> 31) {
+			cpu->shifterOperand = 0xFFFFFFFF;
+			cpu->shifterCarryOut = 1;
+		} else {
+			cpu->shifterOperand = 0;
+			cpu->shifterCarryOut = 0;
+		}
 	} else {
-		cpu->shifterOperand = 0;
-		cpu->shifterCarryOut = 0;
+		int immediate = (opcode & 0x00000F80) >> 7;
+		if (immediate) {
+			cpu->shifterOperand = cpu->gprs[rm] >> immediate;
+			cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
+		} else {
+			cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
+			cpu->shifterOperand = cpu->shifterCarryOut;
+		}
 	}
 }
 
 static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;
-	int immediate = (opcode & 0x00000F80) >> 7;
-	if (immediate) {
-		cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
-		cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
+	if (opcode & 0x00000010) {
+		int rs = (opcode >> 8) & 0x0000000F;
+		++cpu->cycles;
+		int shift = cpu->gprs[rs];
+		if (rs == ARM_PC) {
+			shift += 4;
+		}
+		shift &= 0xFF;
+		int shiftVal =  cpu->gprs[rm];
+		if (rm == ARM_PC) {
+			shiftVal += 4;
+		}
+		int rotate = shift & 0x1F;
+		if (!shift) {
+			cpu->shifterOperand = shiftVal;
+			cpu->shifterCarryOut = cpu->cpsr.c;
+		} else if (rotate) {
+			cpu->shifterOperand = ROR(shiftVal, rotate);
+			cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
+		} else {
+			cpu->shifterOperand = shiftVal;
+			cpu->shifterCarryOut = ARM_SIGN(shiftVal);
+		}
 	} else {
-		// RRX
-		cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
-		cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
-	}
-}
-
-static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
-	int rm = opcode & 0x0000000F;
-	int rs = (opcode >> 8) & 0x0000000F;
-	++cpu->cycles;
-	int shift = cpu->gprs[rs];
-	if (rs == ARM_PC) {
-		shift += 4;
-	}
-	shift &= 0xFF;
-	int shiftVal =  cpu->gprs[rm];
-	if (rm == ARM_PC) {
-		shiftVal += 4;
-	}
-	int rotate = shift & 0x1F;
-	if (!shift) {
-		cpu->shifterOperand = shiftVal;
-		cpu->shifterCarryOut = cpu->cpsr.c;
-	} else if (rotate) {
-		cpu->shifterOperand = ROR(shiftVal, rotate);
-		cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
-	} else {
-		cpu->shifterOperand = shiftVal;
-		cpu->shifterCarryOut = ARM_SIGN(shiftVal);
+		int immediate = (opcode & 0x00000F80) >> 7;
+		if (immediate) {
+			cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
+			cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
+		} else {
+			// RRX
+			cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
+			cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
+		}
 	}
 }
 
@@ -293,32 +289,20 @@
 #define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
 
 #define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
-	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
 	DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
 
 #define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \