M CHANGES → CHANGES

@@ -31,6 +31,7 @@ - GBA Memory: Fix alignment of open bus 8- and 16-bit loads
  - GBA Thread: Fix possible hang when loading an archive
  - Perf: Fix crash when the GBA thread fails to start
  - SDL: Properly clean up if a game doesn't launch
+ - Debugger: Disassembly now lists PSR bitmasks (fixes #191)
 Misc:
  - GBA Audio: Change internal audio sample buffer from 32-bit to 16-bit samples
  - GBA Memory: Simplify memory API and use fixed bus width

M src/arm/decoder-arm.c → src/arm/decoder-arm.c

@@ -386,6 +386,7 @@
 DEFINE_DECODER_ARM(MSR, MSR,
 	info->affectsCPSR = 1;
 	info->op1.reg = ARM_CPSR;
+	info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
 	info->op2.reg = opcode & 0x0000000F;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |
@@ -393,6 +394,7 @@ ARM_OPERAND_REGISTER_2;)
 
 DEFINE_DECODER_ARM(MSRR, MSR,
 	info->op1.reg = ARM_SPSR;
+	info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
 	info->op2.reg = opcode & 0x0000000F;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |
@@ -402,6 +404,7 @@ DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
 	info->affectsCPSR = 1;
 	info->op1.reg = (opcode >> 12) & 0xF;
 	info->op2.reg = ARM_CPSR;
+	info->op2.psrBits = 0;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_REGISTER_2;)
@@ -410,6 +413,7 @@ DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
 	info->affectsCPSR = 1;
 	info->op1.reg = (opcode >> 12) & 0xF;
 	info->op2.reg = ARM_SPSR;
+	info->op2.psrBits = 0;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |
 		ARM_OPERAND_REGISTER_2;)
@@ -419,6 +423,7 @@ int rotate = (opcode & 0x00000F00) >> 7;
 	int32_t operand = ROR(opcode & 0x000000FF, rotate);
 	info->affectsCPSR = 1;
 	info->op1.reg = ARM_CPSR;
+	info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
 	info->op2.immediate = operand;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |
@@ -429,6 +434,7 @@ int rotate = (opcode & 0x00000F00) >> 7;
 	int32_t operand = ROR(opcode & 0x000000FF, rotate);
 	info->affectsCPSR = 1;
 	info->op1.reg = ARM_SPSR;
+	info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
 	info->op2.immediate = operand;
 	info->operandFormat = ARM_OPERAND_REGISTER_1 |
 		ARM_OPERAND_AFFECTED_1 |

M src/arm/decoder.c → src/arm/decoder.c

@@ -18,6 +18,7 @@ blen -= AMOUNT;
 
 static int _decodeRegister(int reg, char* buffer, int blen);
 static int _decodeRegisterList(int list, char* buffer, int blen);
+static int _decodePSR(int bits, char* buffer, int blen);
 static int _decodePCRelative(uint32_t address, uint32_t pc, char* buffer, int blen);
 static int _decodeMemory(struct ARMMemoryAccess memory, int pc, char* buffer, int blen);
 static int _decodeShift(union ARMOperand operand, bool reg, char* buffer, int blen);
@@ -110,6 +111,32 @@ ADVANCE(written);
 	}
 	strncpy(buffer, "}", blen - 1);
 	ADVANCE(1);
+	return total;
+}
+
+static int _decodePSR(int psrBits, char* buffer, int blen) {
+	if (!psrBits) {
+		return 0;
+	}
+	int total = 0;
+	strncpy(buffer, "_", blen - 1);
+	ADVANCE(1);
+	if (psrBits & ARM_PSR_C) {
+		strncpy(buffer, "c", blen - 1);
+		ADVANCE(1);
+	}
+	if (psrBits & ARM_PSR_X) {
+		strncpy(buffer, "x", blen - 1);
+		ADVANCE(1);
+	}
+	if (psrBits & ARM_PSR_S) {
+		strncpy(buffer, "s", blen - 1);
+		ADVANCE(1);
+	}
+	if (psrBits & ARM_PSR_F) {
+		strncpy(buffer, "f", blen - 1);
+		ADVANCE(1);
+	}
 	return total;
 }
 
@@ -370,6 +397,10 @@ ADVANCE(written);
 		} else if (info->operandFormat & ARM_OPERAND_REGISTER_1) {
 			written = _decodeRegister(info->op1.reg, buffer, blen);
 			ADVANCE(written);
+			if (info->op1.reg > ARM_PC) {
+				written = _decodePSR(info->op1.psrBits, buffer, blen);
+				ADVANCE(written);
+			}
 		}
 		if (info->operandFormat & ARM_OPERAND_SHIFT_REGISTER_1) {
 			written = _decodeShift(info->op1, true, buffer, blen);

M src/arm/decoder.h → src/arm/decoder.h

@@ -62,6 +62,12 @@ #define ARM_MEMORY_DECREMENT_BEFORE  0x0200
 #define ARM_MEMORY_INCREMENT_BEFORE  0x0300
 #define ARM_MEMORY_SPSR_SWAP         0x0400
 
+#define ARM_PSR_C 1
+#define ARM_PSR_X 2
+#define ARM_PSR_S 4
+#define ARM_PSR_F 8
+#define ARM_PSR_MASK 0xF
+
 #define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
 
 enum ARMCondition {
@@ -99,6 +105,7 @@ uint8_t shifterOp;
 		union {
 			uint8_t shifterReg;
 			uint8_t shifterImm;
+			uint8_t psrBits;
 		};
 	};
 	int32_t immediate;