all repos — mgba @ 99d7c588e754fbcb60c28197b412c4473efde1ea

mGBA Game Boy Advance Emulator

Merge branch 'master' into medusa
Vicki Pfau vi@endrift.com
Wed, 29 Jul 2020 21:41:38 -0700
commit

99d7c588e754fbcb60c28197b412c4473efde1ea

parent

2d8c926069a15c6e1302162439b58d5a72afcac6

5 files changed, 55 insertions(+), 45 deletions(-)

jump to
M CHANGES → CHANGES 
@@ -68,6 +68,7 @@ Other fixes:
  - All: Improve export headers (fixes mgba.io/i/1738)
  - All: Correct format strings for some numbers on Windows (fixes mgba.io/i/1794)
  - All: Correct more format strings on Windows (fixes mgba.io/i/1817)
+ - ARM: Fix decoder detection of branches with ALU and LDR instrctions
  - CMake: Fix build with libzip 1.7
  - Core: Ensure ELF regions can be written before trying
  - Debugger: Don't skip undefined instructions when debugger attached

@@ -94,6 +95,7 @@ - Qt: Add hex index to palette view
  - Qt: Add transformation matrix info to sprite view
  - Qt: Add per-page scrolling to memory view (fixes mgba.io/i/1795)
  - Qt: Add setting to display ROM filename in title (closes mgba.io/i/1784)
+ - Util: Reset vector size on deinit
 
 0.8.2: (2020-06-14)
 Emulation fixes:
M include/mgba-util/vector.h → include/mgba-util/vector.h 
@@ -47,6 +47,7 @@ void NAME ## Deinit(struct NAME* vector) { \
 		free(vector->vector); \
 		vector->vector = 0; \
 		vector->capacity = 0; \
+		vector->size = 0; \
 	} \
 	TYPE* NAME ## GetPointer(struct NAME* vector, size_t location) { \
 		return &vector->vector[location]; \
M src/arm/decoder-arm.c → src/arm/decoder-arm.c 
@@ -109,7 +109,7 @@ info->op2 = info->op3; \
 			info->operandFormat |= info->operandFormat >> 8; \
 			info->operandFormat &= ~ARM_OPERAND_3; \
 		} \
-		if (info->op1.reg == ARM_PC) { \
+		if (info->op1.reg == ARM_PC && (OTHER_AFFECTED & ARM_OPERAND_AFFECTED_1)) { \
 			info->branchType = ARM_BRANCH_INDIRECT; \
 		})
 

@@ -173,71 +173,78 @@ #define DEFINE_LONG_MULTIPLY_DECODER_ARM(NAME) \
 	DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0) \
 	DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1)
 
-#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE) \
+#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_DECODER_ARM(NAME, MNEMONIC, \
 		info->op1.reg = (opcode >> 12) & 0xF; \
 		info->memory.baseReg = (opcode >> 16) & 0xF; \
 		info->memory.width = TYPE; \
 		info->operandFormat = ARM_OPERAND_REGISTER_1 | \
-			ARM_OPERAND_AFFECTED_1 | /* TODO: Remove this for STR */ \
+			OTHER_AFFECTED | \
 			ARM_OPERAND_MEMORY_2; \
 		info->memory.format = ARM_MEMORY_REGISTER_BASE | ADDRESSING_MODE; \
 		ADDRESSING_DECODING; \
+		if (info->op1.reg == ARM_PC && (OTHER_AFFECTED & ARM_OPERAND_AFFECTED_1)) { \
+			info->branchType = ARM_BRANCH_INDIRECT; \
+		} \
+		if ((info->memory.format & (ARM_MEMORY_WRITEBACK | ARM_MEMORY_REGISTER_OFFSET)) == (ARM_MEMORY_WRITEBACK | ARM_MEMORY_REGISTER_OFFSET) && \
+		    info->memory.offset.reg == ARM_PC) { \
+			info->branchType = ARM_BRANCH_INDIRECT; \
+		} \
 		CYCLES;)
 
-#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
+#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
 		ARM_MEMORY_POST_INCREMENT | \
 		ARM_MEMORY_WRITEBACK | \
 		ARM_MEMORY_OFFSET_SUBTRACT, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
 		ARM_MEMORY_POST_INCREMENT | \
 		ARM_MEMORY_WRITEBACK, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## P, MNEMONIC, \
 		ARM_MEMORY_OFFSET_SUBTRACT, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PW, MNEMONIC, \
 		ARM_MEMORY_PRE_INCREMENT | \
 		ARM_MEMORY_WRITEBACK | \
 		ARM_MEMORY_OFFSET_SUBTRACT, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PU, MNEMONIC, \
 		0, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PUW, MNEMONIC, \
 		ARM_MEMORY_WRITEBACK, \
-		ADDRESSING_MODE, CYCLES, TYPE)
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 
-#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
+#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE, OTHER_AFFECTED)
 
-#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, CYCLES, TYPE)
+#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, CYCLES, TYPE, OTHER_AFFECTED)
 
-#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
+#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
 		ARM_MEMORY_POST_INCREMENT | \
 		ARM_MEMORY_WRITEBACK | \
 		ARM_MEMORY_OFFSET_SUBTRACT, \
-		ADDRESSING_MODE, CYCLES, TYPE) \
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED) \
 	DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
 		ARM_MEMORY_POST_INCREMENT | \
 		ARM_MEMORY_WRITEBACK, \
-		ADDRESSING_MODE, CYCLES, TYPE)
+		ADDRESSING_MODE, CYCLES, TYPE, OTHER_AFFECTED)
 
-#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
-	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
+#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE, OTHER_AFFECTED) \
+	DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE, OTHER_AFFECTED)
 
 #define DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME, MNEMONIC, DIRECTION, WRITEBACK) \
 	DEFINE_DECODER_ARM(NAME, MNEMONIC, \

@@ -327,22 +334,22 @@ DEFINE_MULTIPLY_DECODER_EX_ARM(SMULWT, SMULWT, 0, 0)
 
 // Begin load/store definitions
 
-DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
-DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRv5, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
-DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRD, LDR, LOAD_CYCLES, ARM_ACCESS_DUALWORD)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
-DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE_CYCLES, ARM_ACCESS_WORD)
-DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRD, STR, STORE_CYCLES, ARM_ACCESS_DUALWORD)
-DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
+DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD_CYCLES, ARM_ACCESS_WORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRv5, LDR, LOAD_CYCLES, ARM_ACCESS_WORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRD, LDR, LOAD_CYCLES, ARM_ACCESS_DUALWORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE_CYCLES, ARM_ACCESS_WORD, ARM_OPERAND_NONE)
+DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE_CYCLES, ARM_ACCESS_BYTE, ARM_OPERAND_NONE)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRD, STR, STORE_CYCLES, ARM_ACCESS_DUALWORD, ARM_OPERAND_NONE)
+DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD, ARM_OPERAND_NONE)
 
-DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
-DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
-DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
-DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
+DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_BYTE, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_WORD, ARM_OPERAND_AFFECTED_1)
+DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_BYTE, ARM_OPERAND_NONE)
+DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_WORD, ARM_OPERAND_NONE)
 
 DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(LDM)
 DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM_NO_S(LDM, v5)
M src/core/rewind.c → src/core/rewind.c 
@@ -161,7 +161,7 @@
 #ifndef DISABLE_THREADING
 THREAD_ENTRY _rewindThread(void* context) {
 	struct mCoreRewindContext* rewindContext = context;
-	ThreadSetName("Rewind Diff Thread");
+	ThreadSetName("Rewind Diffing");
 	MutexLock(&rewindContext->mutex);
 	while (rewindContext->onThread) {
 		while (!rewindContext->ready && rewindContext->onThread) {
M src/feature/thread-proxy.c → src/feature/thread-proxy.c 
@@ -178,7 +178,7 @@ }
 
 static THREAD_ENTRY _proxyThread(void* logger) {
 	struct mVideoThreadProxy* proxyRenderer = logger;
-	ThreadSetName("Proxy Renderer Thread");
+	ThreadSetName("Proxy Rendering");
 
 	MutexLock(&proxyRenderer->mutex);
 	ConditionWake(&proxyRenderer->fromThreadCond);