M src/arm/decoder-arm.c → src/arm/decoder-arm.c

@@ -392,6 +392,7 @@ DECLARE_ARM_EMITTER_BLOCK(_ARMDecode)
 };
 
 void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
+	info->execMode = MODE_ARM;
 	info->opcode = opcode;
 	info->branches = 0;
 	info->traps = 0;

M src/arm/decoder-thumb.c → src/arm/decoder-thumb.c

@@ -312,6 +312,7 @@ DECLARE_THUMB_EMITTER_BLOCK(_ThumbDecode)
 };
 
 void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info) {
+	info->execMode = MODE_THUMB;
 	info->opcode = opcode;
 	info->branches = 0;
 	info->traps = 0;

M src/arm/decoder.c → src/arm/decoder.c

@@ -247,6 +247,22 @@ case ARM_MN_STR:
 	case ARM_MN_SWP:
 		flags = _armAccessTypeStrings[info->memory.width];
 		break;
+	case ARM_MN_ADD:
+	case ARM_MN_ADC:
+	case ARM_MN_AND:
+	case ARM_MN_BIC:
+	case ARM_MN_EOR:
+	case ARM_MN_MOV:
+	case ARM_MN_MVN:
+	case ARM_MN_ORR:
+	case ARM_MN_RSB:
+	case ARM_MN_RSC:
+	case ARM_MN_SBC:
+	case ARM_MN_SUB:
+		if (info->affectsCPSR && info->execMode == MODE_ARM) {
+			flags = "s";
+		}
+		break;
 	default:
 		break;
 	}

M src/arm/decoder.h → src/arm/decoder.h

@@ -1,6 +1,8 @@
 #ifndef ARM_DECODER_H
 #define ARM_DECODER_H
 
+#include "arm.h"
+
 #include <stdint.h>
 
 // Bit 0: a register is involved with this operand
@@ -165,6 +167,7 @@ ARM_MN_MAX
 };
 
 struct ARMInstructionInfo {
+	enum ExecutionMode execMode;
 	uint32_t opcode;
 	enum ARMMnemonic mnemonic;
 	union ARMOperand op1;