all repos — mgba @ a6d87bbfb99c15b110ba471809aefc8b611b3361

mGBA Game Boy Advance Emulator

Better cycle counting for STR
Jeffrey Pfau jeffrey@endrift.com
Sat, 11 May 2013 18:01:16 -0700
commit

a6d87bbfb99c15b110ba471809aefc8b611b3361

parent

b6361cdfa942d2bdc0f759eebceb4227efe991cd

4 files changed, 79 insertions(+), 55 deletions(-)

jump to
M src/arm/arm.h → src/arm/arm.h 
@@ -81,6 +81,8 @@ uint32_t* activeRegion;
 	uint32_t activeMask;
 	uint32_t activePrefetchCycles32;
 	uint32_t activePrefetchCycles16;
+	uint32_t activeNonseqCycles32;
+	uint32_t activeNonseqCycles16;
 	void (*setActiveRegion)(struct ARMMemory*, uint32_t address);
 	int (*waitMultiple)(struct ARMMemory*, uint32_t startAddress, int count);
 };
M src/arm/isa-arm.c → src/arm/isa-arm.c 
@@ -9,6 +9,8 @@ PSR_PRIV_MASK = 0x000000CF,
 	PSR_STATE_MASK = 0x00000020
 };
 
+#define ARM_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles32)
+
 // Addressing mode 1
 static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;

@@ -203,85 +205,85 @@ } else {
 		switch (condition) {
 		case 0x0:
 			if (!ARM_COND_EQ) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x1:
 			if (!ARM_COND_NE) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x2:
 			if (!ARM_COND_CS) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x3:
 			if (!ARM_COND_CC) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x4:
 			if (!ARM_COND_MI) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x5:
 			if (!ARM_COND_PL) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x6:
 			if (!ARM_COND_VS) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x7:
 			if (!ARM_COND_VC) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x8:
 			if (!ARM_COND_HI) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0x9:
 			if (!ARM_COND_LS) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0xA:
 			if (!ARM_COND_GE) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0xB:
 			if (!ARM_COND_LT) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0xC:
 			if (!ARM_COND_GT) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;
 		case 0xD:
 			if (!ARM_COND_LE) {
-				cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
+				cpu->cycles += ARM_PREFETCH_CYCLES;
 				return;
 			}
 			break;

@@ -356,10 +358,15 @@ if (rd == ARM_PC) { \
 		ARM_WRITE_PC; \
 	}
 
+#define ARM_STORE_POST_BODY \
+	currentCycles -= ARM_PREFETCH_CYCLES; \
+	currentCycles += 1 + cpu->memory->activeNonseqCycles32;
+
 #define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
 	static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
-		cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
+		int currentCycles = ARM_PREFETCH_CYCLES; \
 		BODY; \
+		cpu->cycles += currentCycles; \
 	}
 
 #define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \

@@ -529,7 +536,7 @@ S_PRE; \
 		LOOP(BODY); \
 		S_POST; \
 		WRITEBACK; \
-		cpu->cycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
+		currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
 		POST_BODY;)
 
 

@@ -648,49 +655,53 @@ // End multiply definitions
 
 // Begin load/store definitions
 
-DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, &cpu->cycles); ARM_LOAD_POST_BODY;)
-DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, &cpu->cycles); ARM_LOAD_POST_BODY;)
-DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, &cpu->cycles); ARM_LOAD_POST_BODY;)
-DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, &cpu->cycles); ARM_LOAD_POST_BODY;)
-DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, &cpu->cycles); ARM_LOAD_POST_BODY;)
-DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], &cpu->cycles))
-DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], &cpu->cycles))
-DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], &cpu->cycles))
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, &currentCycles); ARM_LOAD_POST_BODY;)
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, &currentCycles); ARM_LOAD_POST_BODY;)
+DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, &currentCycles); ARM_LOAD_POST_BODY;)
+DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, &currentCycles); ARM_LOAD_POST_BODY;)
+DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, &currentCycles); ARM_LOAD_POST_BODY;)
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], &currentCycles); ARM_STORE_POST_BODY;)
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], &currentCycles); ARM_STORE_POST_BODY;)
+DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], &currentCycles); ARM_STORE_POST_BODY;)
 
 DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
 	enum PrivilegeMode priv = cpu->privilegeMode;
 	ARMSetPrivilegeMode(cpu, MODE_USER);
-	cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, &cpu->cycles);
+	cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, &currentCycles);
 	ARMSetPrivilegeMode(cpu, priv);
 	ARM_LOAD_POST_BODY;)
 
 DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
 	enum PrivilegeMode priv = cpu->privilegeMode;
 	ARMSetPrivilegeMode(cpu, MODE_USER);
-	cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, &cpu->cycles);
+	cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, &currentCycles);
 	ARMSetPrivilegeMode(cpu, priv);
 	ARM_LOAD_POST_BODY;)
 
 DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
 	enum PrivilegeMode priv = cpu->privilegeMode;
 	ARMSetPrivilegeMode(cpu, MODE_USER);
-	cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], &cpu->cycles);
-	ARMSetPrivilegeMode(cpu, priv);)
+	cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], &currentCycles);
+	ARMSetPrivilegeMode(cpu, priv);
+	ARM_STORE_POST_BODY;)
 
 DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
 	enum PrivilegeMode priv = cpu->privilegeMode;
 	ARMSetPrivilegeMode(cpu, MODE_USER);
-	cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], &cpu->cycles);
-	ARMSetPrivilegeMode(cpu, priv);)
+	cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], &currentCycles);
+	ARMSetPrivilegeMode(cpu, priv);
+	ARM_STORE_POST_BODY;)
 
 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
 	cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr, 0);,
-	++cpu->cycles;
+	++currentCycles;
 	if (rs & 0x8000) {
 		ARM_WRITE_PC;
 	})
 
-DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);, )
+DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
+	cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
+	currentCycles -= ARM_PREFETCH_CYCLES)
 
 DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
 DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
M src/arm/isa-thumb.c → src/arm/isa-thumb.c 
@@ -44,6 +44,12 @@ int m = M; \
 	D = M - N; \
 	THUMB_SUBTRACTION_S(m, n, D)
 
+#define THUMB_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles16)
+
+#define THUMB_STORE_POST_BODY \
+	currentCycles -= THUMB_PREFETCH_CYCLES; \
+	currentCycles += 1 + cpu->memory->activeNonseqCycles16;
+
 #define APPLY(F, ...) F(__VA_ARGS__)
 
 #define COUNT_1(EMITTER, PREFIX, ...) \

@@ -94,8 +100,9 @@ EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
 
 #define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
 	static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) {  \
-		cpu->cycles += 1 + cpu->memory->activePrefetchCycles16; \
+		int currentCycles = THUMB_PREFETCH_CYCLES; \
 		BODY; \
+		cpu->cycles += currentCycles; \
 	}
 
 #define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \

@@ -141,12 +148,12 @@ cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
 	}
 	THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
 
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4, &cpu->cycles))
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate, &cpu->cycles))
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2, &cpu->cycles))
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], &cpu->cycles))
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd], &cpu->cycles))
-DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], &cpu->cycles))
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4, &currentCycles))
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate, &currentCycles))
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2, &currentCycles))
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
+DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
 
 #define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
 	DEFINE_INSTRUCTION_THUMB(NAME, \

@@ -313,9 +320,9 @@
 #define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
 	COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
 
-DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, &cpu->cycles))
-DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate, &cpu->cycles))
-DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], &cpu->cycles))
+DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, &currentCycles))
+DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate, &currentCycles))
+DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
 
 DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
 DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)

@@ -330,14 +337,14 @@
 #define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
 	COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
 
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &cpu->cycles))
-DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &cpu->cycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles))
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
+DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
 
 #define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
 	DEFINE_INSTRUCTION_THUMB(NAME, \

@@ -357,7 +364,7 @@ ++total; \
 			} \
 		} \
 		POST_BODY; \
-		cpu->cycles += cpu->memory->waitMultiple(cpu->memory, address, total); \
+		currentCycles += cpu->memory->waitMultiple(cpu->memory, address, total); \
 		WRITEBACK;)
 
 #define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
M src/gba/gba-memory.c → src/gba/gba-memory.c 
@@ -81,9 +81,11 @@
 static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
 	struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
 
-	memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[address >> BASE_OFFSET];
-	memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[address >> BASE_OFFSET];
 	gbaMemory->activeRegion = address >> BASE_OFFSET;
+	memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
+	memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
+	memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
+	memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
 	switch (address & ~OFFSET_MASK) {
 	case BASE_BIOS:
 		memory->activeRegion = gbaMemory->bios;

@@ -472,8 +474,10 @@ memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
 		memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
 	}
 
-	memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
-	memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
+	memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
+	memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
+	memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
+	memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
 }
 
 int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {