Overwrite IF while attempting to IntrWait
Jeffrey Pfau jeffrey@endrift.com
Sun, 05 May 2013 00:44:30 -0700
3 files changed,
10 insertions(+),
8 deletions(-)
M
src/gba/gba-bios.c
→
src/gba/gba-bios.c
@@ -179,7 +179,6 @@ gba->memory.io[REG_IME >> 1] = 1;
if (!gba->cpu.gprs[0] && gba->memory.io[REG_IF >> 1] & gba->cpu.gprs[1]) { break; } - gba->memory.io[REG_IF >> 1] = 0; ARMRaiseSWI(&gba->cpu); break; case 0x6:
M
src/gba/hle-bios.c
→
src/gba/hle-bios.c
@@ -1,6 +1,5 @@
#include "hle-bios.h" -const unsigned int hleBiosLength = 216; const unsigned char hleBios[] = { 0x06, 0x00, 0x00, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x05, 0x00, 0x00, 0xea, 0xfe, 0xff, 0xff, 0xea, 0xfe, 0xff, 0xff, 0xea, 0x00, 0x00, 0xa0, 0xe1,@@ -14,10 +13,12 @@ 0x0f, 0x50, 0xbd, 0xe8, 0x04, 0xf0, 0x5e, 0xe2, 0x04, 0x40, 0x2d, 0xe9,
0x04, 0xd0, 0x4d, 0xe2, 0xb0, 0x10, 0xcd, 0xe1, 0x01, 0x23, 0xa0, 0xe3, 0x02, 0x2c, 0x82, 0xe2, 0xb0, 0x00, 0xd2, 0xe1, 0xb2, 0x00, 0xcd, 0xe1, 0xb0, 0x10, 0xdd, 0xe1, 0x01, 0x10, 0x80, 0xe1, 0xb0, 0x10, 0xc2, 0xe1, - 0x1f, 0x00, 0xa0, 0xe3, 0x00, 0xf0, 0x29, 0xe1, 0x00, 0x00, 0x02, 0xef, - 0xd3, 0x00, 0xa0, 0xe3, 0x00, 0xf0, 0x29, 0xe1, 0x01, 0x03, 0xa0, 0xe3, - 0xb8, 0x20, 0x50, 0xe1, 0xb0, 0x10, 0xdd, 0xe1, 0x02, 0x10, 0x11, 0xe0, - 0x02, 0x10, 0x21, 0x10, 0xb8, 0x10, 0x40, 0x11, 0xb2, 0x00, 0xdd, 0xe1, - 0x01, 0x13, 0xa0, 0xe3, 0x02, 0x1c, 0x81, 0xe2, 0xb0, 0x00, 0xc1, 0xe1, - 0xe8, 0xff, 0xff, 0x0a, 0x04, 0xd0, 0x8d, 0xe2, 0x04, 0x80, 0xbd, 0xe8 + 0x00, 0x00, 0xe0, 0xe3, 0xb2, 0x00, 0xc2, 0xe1, 0x1f, 0x00, 0xa0, 0xe3, + 0x00, 0xf0, 0x29, 0xe1, 0x00, 0x00, 0x02, 0xef, 0xd3, 0x00, 0xa0, 0xe3, + 0x00, 0xf0, 0x29, 0xe1, 0x01, 0x03, 0xa0, 0xe3, 0xb8, 0x20, 0x50, 0xe1, + 0xb0, 0x10, 0xdd, 0xe1, 0x02, 0x10, 0x11, 0xe0, 0x02, 0x10, 0x21, 0x10, + 0xb8, 0x10, 0x40, 0x11, 0xb2, 0x00, 0xdd, 0xe1, 0x01, 0x13, 0xa0, 0xe3, + 0x02, 0x1c, 0x81, 0xe2, 0xb0, 0x00, 0xc1, 0xe1, 0xe6, 0xff, 0xff, 0x0a, + 0x04, 0xd0, 0x8d, 0xe2, 0x04, 0x80, 0xbd, 0xe8 }; +const unsigned int hleBiosLength = 224;
M
src/gba/hle-bios.s
→
src/gba/hle-bios.s
@@ -47,6 +47,8 @@ strh r0, [sp, #2]
ldrh r1, [sp, #0] orr r1, r0, r1 strh r1, [r2, #0] +mov r0, #0xFFFFFFFF +strh r0, [r2, #2] mov r0, #0x1F msr cpsr, r0 swi #0x020000