ARM: Add comments marking instruction hex
Vicki Pfau vi@endrift.com
Tue, 11 Apr 2017 16:52:27 -0700
2 files changed,
363 insertions(+),
363 deletions(-)
M
include/mgba/internal/arm/emitter-arm.h
→
include/mgba/internal/arm/emitter-arm.h
@@ -102,279 +102,279 @@ #define DECLARE_ARM_SWI_BLOCK(EMITTER) \
DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI)) #define DECLARE_ARM_EMITTER_BLOCK(EMITTER, V) \ - DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \ - DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \ - DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \ - DECLARE_INSTRUCTION_ARM(EMITTER, BX), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \ - DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \ - DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, CLZ), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , , , V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , U, , V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , , V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , W, V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, , V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, W, V), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \ - DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , , , V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , U, , V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , , V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , W, V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, , V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \ - DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, W, V), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \ - DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, , V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, W, V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, , V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, W, V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, , V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, W, V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, , V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, W, V), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \ - DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \ - DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \ - DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \ - DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \ - DECLARE_ARM_SWI_BLOCK(EMITTER) + /* -00---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \ + /* -01---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \ + /* -02---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \ + /* -03---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \ + /* -04---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \ + /* -05---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \ + /* -06---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \ + /* -07---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \ + /* -08---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \ + /* -09---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \ + /* -0A---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \ + /* -0B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \ + /* -0C---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \ + /* -0D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \ + /* -0E---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \ + /* -0F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \ + /* -10---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \ + /* -10---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -10---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \ + /* -10---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -10---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \ + /* -10---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -10---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -10---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -10---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -11---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \ + /* -12---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \ + /* -12---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, BX), \ + /* -12---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---3- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -12---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \ + /* -12---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -12---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -12---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \ + /* -12---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -12---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -12---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -12---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -13---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \ + /* -14---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \ + /* -14---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---8- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \ + /* -14---A- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \ + /* -14---C- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---E- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -14---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -15---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \ + /* -16---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \ + /* -16---1- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, CLZ), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -16---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -16---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -16---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \ + /* -16---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -16---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -16---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \ + /* -16---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + /* -17---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \ + /* -18---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \ + /* -19---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \ + /* -1A---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \ + /* -1B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \ + /* -1C---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \ + /* -1D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \ + /* -1E---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \ + /* -1F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \ + /* -20---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \ + /* -21---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \ + /* -22---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \ + /* -23---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \ + /* -24---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \ + /* -25---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \ + /* -26---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \ + /* -27---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \ + /* -28---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \ + /* -29---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \ + /* -2A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \ + /* -2B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \ + /* -2C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \ + /* -2D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \ + /* -2E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \ + /* -2F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \ + /* -30---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \ + /* -31---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \ + /* -32---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \ + /* -33---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \ + /* -34---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \ + /* -35---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \ + /* -36---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \ + /* -37---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \ + /* -38---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \ + /* -39---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \ + /* -3A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \ + /* -3B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \ + /* -3C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \ + /* -3D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \ + /* -3E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \ + /* -3F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \ + /* -40---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \ + /* -41---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , , , V), \ + /* -42---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \ + /* -43---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \ + /* -44---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \ + /* -45---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \ + /* -46---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \ + /* -47---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \ + /* -48---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \ + /* -49---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , U, , V), \ + /* -4A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \ + /* -4B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \ + /* -4C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \ + /* -4D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \ + /* -4E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \ + /* -4F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \ + /* -50---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \ + /* -51---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , , V), \ + /* -52---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \ + /* -53---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , W, V), \ + /* -54---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \ + /* -55---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \ + /* -56---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \ + /* -57---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \ + /* -58---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \ + /* -59---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, , V), \ + /* -5A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \ + /* -5B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, W, V), \ + /* -5C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \ + /* -5D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \ + /* -5E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \ + /* -5F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \ + /* -60---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \ + /* -61---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , , , V), \ + /* -62---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \ + /* -63---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \ + /* -64---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \ + /* -65---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \ + /* -66---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \ + /* -67---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \ + /* -68---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \ + /* -69---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , U, , V), \ + /* -6A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \ + /* -6B---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \ + /* -6C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \ + /* -6D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \ + /* -6E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \ + /* -6F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \ + /* -70---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \ + /* -71---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , , V), \ + /* -72---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \ + /* -73---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , W, V), \ + /* -74---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \ + /* -75---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \ + /* -76---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \ + /* -77---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \ + /* -78---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \ + /* -79---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, , V), \ + /* -7A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \ + /* -7B---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, W, V), \ + /* -7C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \ + /* -7D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \ + /* -7E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \ + /* -7F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \ + /* -80---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \ + /* -81---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, , V), \ + /* -82---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \ + /* -83---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, W, V), \ + /* -84---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \ + /* -85---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \ + /* -86---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \ + /* -87---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \ + /* -88---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \ + /* -89---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, , V), \ + /* -8A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \ + /* -8B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, W, V), \ + /* -8C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \ + /* -8D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \ + /* -8E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \ + /* -8F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \ + /* -90---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \ + /* -91---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, , V), \ + /* -92---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \ + /* -93---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, W, V), \ + /* -94---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \ + /* -95---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \ + /* -96---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \ + /* -97---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \ + /* -98---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \ + /* -99---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, , V), \ + /* -9A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \ + /* -9B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, W, V), \ + /* -9C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \ + /* -9D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \ + /* -9E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \ + /* -9F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \ + /* -AX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \ + /* -BX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \ + /* -C0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \ + /* -C1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \ + /* -C2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \ + /* -C3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \ + /* -C4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \ + /* -C5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \ + /* -C6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \ + /* -C7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \ + /* -C8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \ + /* -C9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \ + /* -CA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \ + /* -CB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \ + /* -CC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \ + /* -CD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \ + /* -CE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \ + /* -CF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \ + /* -D0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \ + /* -D1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \ + /* -D2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \ + /* -D3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \ + /* -D4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \ + /* -D5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \ + /* -D6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \ + /* -D7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \ + /* -D8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \ + /* -D9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \ + /* -DA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \ + /* -DB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \ + /* -DC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \ + /* -DD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \ + /* -DE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \ + /* -DF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \ + /* -EX---X- */ DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \ + /* -RX---X- */ DECLARE_ARM_SWI_BLOCK(EMITTER) #define DECLARE_ARM_F_EMITTER_BLOCK(EMITTER, V) \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \ - DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ - DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), + /* F0X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F1X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F2X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F3X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F4X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F5X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F6X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F7X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F8X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* F9X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* FAX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \ + /* FBX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \ + /* FCX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* FDX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* FEX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \ + /* FFX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), #endif
M
include/mgba/internal/arm/emitter-thumb.h
→
include/mgba/internal/arm/emitter-thumb.h
@@ -18,96 +18,96 @@ DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11) #define DECLARE_THUMB_EMITTER_BLOCK(EMITTER, V) \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1))), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1)), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2))), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \ - DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \ - DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \ - DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \ - MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX2), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5), \ - MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX2), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3))), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STR2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH)), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR3))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6))), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \ - DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \ - DO_4(MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR), DECLARE_INSTRUCTION_THUMB(EMITTER, POPRv4), V >= 5)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA))), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ - DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \ - DO_8(DO_4(MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX1), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \ - DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \ + /* 00X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1))), \ + /* 08X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1))), \ + /* 10X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1))), \ + /* 18X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3)), \ + /* 1AX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3)), \ + /* 1CX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1)), \ + /* 1EX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1)), \ + /* 20X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1))), \ + /* 28X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1))), \ + /* 30X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2))), \ + /* 38X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2))), \ + /* 400- */ DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \ + /* 404- */ DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \ + /* 408- */ DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \ + /* 40C- */ DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \ + /* 410- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \ + /* 414- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \ + /* 418- */ DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \ + /* 41C- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \ + /* 420- */ DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \ + /* 424- */ DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \ + /* 428- */ DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \ + /* 42C- */ DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \ + /* 430- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \ + /* 434- */ DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \ + /* 438- */ DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \ + /* 43C- */ DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \ + /* 44X- */ DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \ + /* 45X- */ DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \ + /* 46X- */ DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \ + /* 470- */ DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \ + /* 474- */ DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \ + /* 478- */ MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX2), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5), \ + /* 47C- */ MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX2), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5), \ + /* 48X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3))), \ + /* 50X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STR2)), \ + /* 52X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2)), \ + /* 54X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2)), \ + /* 56X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB)), \ + /* 58X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2)), \ + /* 5AX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2)), \ + /* 5CX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2)), \ + /* 5EX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH)), \ + /* 60X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR1))), \ + /* 68X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1))), \ + /* 70X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1))), \ + /* 78X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1))), \ + /* 80X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1))), \ + /* 88X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1))), \ + /* 90X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR3))), \ + /* 98X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4))), \ + /* A0X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5))), \ + /* A8X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6))), \ + /* B00- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \ + /* B04- */ DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \ + /* B08- */ DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \ + /* B0C- */ DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \ + /* B1X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* B2X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* B3X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* B4X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \ + /* B5X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \ + /* B6X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* B8X- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* BAX- */ DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* BCX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \ + /* BDX- */ DO_4(MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR), DECLARE_INSTRUCTION_THUMB(EMITTER, POPRv4), V >= 5)), \ + /* BEX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \ + /* BFX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* C0X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA))), \ + /* C8X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA))), \ + /* D0X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \ + /* D1X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \ + /* D2X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \ + /* D3X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \ + /* D4X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \ + /* D5X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \ + /* D6X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \ + /* D7X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \ + /* D8X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \ + /* D9X- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \ + /* DAX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \ + /* DBX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \ + /* DCX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \ + /* DDX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \ + /* DEX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \ + /* DFX- */ DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \ + /* E0X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \ + /* E8X- */ DO_8(DO_4(MIN_V(DECLARE_INSTRUCTION_THUMB(EMITTER, BLX1), DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), V >= 5))), \ + /* F0X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \ + /* F8X- */ DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \ #endif