Stub out branch instructions
Jeffrey Pfau jeffrey@endrift.com
Sat, 06 Apr 2013 19:22:14 -0700
1 files changed,
33 insertions(+),
4 deletions(-)
jump to
M
src/arm.c
→
src/arm.c
@@ -375,6 +375,14 @@ DEFINE_INSTRUCTION_ARM(SWPB,)
// End load/store definitions +// Begin branch definitions + +DEFINE_INSTRUCTION_ARM(B,) +DEFINE_INSTRUCTION_ARM(BL,) +DEFINE_INSTRUCTION_ARM(BX,) + +// End branch definitions + // TODO DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode DEFINE_INSTRUCTION_ARM(MSR,)@@ -436,6 +444,12 @@ #define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, NAME, MODE, W) \
DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)), \ DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## MODE ## W)) +#define DECLARE_ARM_BRANCH_BLOCK(COND, NAME) \ + DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \ + DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \ + DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \ + DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))) + #define LDRHW ILL #define LDRSBW ILL #define LDRSHW ILL@@ -472,7 +486,22 @@ DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRHIUW, ILL, ILL), \
DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \ DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \ - DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHPW, ILL, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, MSR), \ + DECLARE_INSTRUCTION_ARM(COND, BX), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, STRHPW), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ + DECLARE_INSTRUCTION_ARM(COND, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \ DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \@@ -613,9 +642,9 @@ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, IB, W), \
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, ), \ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, ), \ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STMS, IB, W), \ - DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W)//, \ - // DECLARE_ARM_BRANCH_BLOCK(COND, B), \ - // DECLARE_ARM_BRANCH_BLOCK(COND, BL), \ + DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDMS, IB, W), \ + DECLARE_ARM_BRANCH_BLOCK(COND, B), \ + DECLARE_ARM_BRANCH_BLOCK(COND, BL)//, \ // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \ // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \ // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \