M CHANGES → CHANGES

@@ -4,6 +4,7 @@ - ARM: Fix ALU reading PC after shifting
  - ARM: Fix STR storing PC after address calculation
  - GBA DMA: Linger last DMA on bus (fixes mgba.io/i/301 and mgba.io/i/1320)
  - GBA Memory: Misaligned SRAM writes are ignored
+ - GBA Memory: Improve gamepak prefetch timing
  - GBA Serialize: Fix serializing DMA transfer register
  - GBA Serialize: Fix audio serialization for desynced FIFOs
  - GBA Serialize: Fix audio DMA timing deserialization

M src/gba/memory.c → src/gba/memory.c

@@ -1626,17 +1626,19 @@ previousLoads = dist >> 1;
 		maxLoads -= previousLoads;
 	}
 
-	int32_t s = cpu->memory.activeSeqCycles16 + 1;
+	int32_t s = cpu->memory.activeSeqCycles16;
 	int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
 
 	// Figure out how many sequential loads we can jam in
-	int32_t stall = s;
+	int32_t stall = s + 1;
 	int32_t loads = 1;
 
 	while (stall < wait && loads < maxLoads) {
 		stall += s;
 		++loads;
 	}
+	memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * (loads + previousLoads - 1);
+
 	if (stall > wait) {
 		// The wait cannot take less time than the prefetch stalls
 		wait = stall;
@@ -1645,10 +1647,9 @@
 	// This instruction used to have an N, convert it to an S.
 	wait -= n2s;
 
-	memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * (loads + previousLoads - 1);
+	// The next |loads|S waitstates disappear entirely, so long as they're all in a row
+	wait -= stall - 1;
 
-	// The next |loads|S waitstates disappear entirely, so long as they're all in a row
-	cpu->cycles -= (s - 1) * loads;
 	return wait;
 }