@@ -41,6 +41,7 @@ - Qt: Don't rebuild library view if style hasn't changed
  - Qt: Redo GameController into multiple classes
  - SDL: Fix 2.0.5 build on macOS under some circumstances
  - Test: Restructure test suite into multiple executables
+ - Python: Integrate tests from cinema test suite
 
 0.6.0: (2017-07-16)
 Features:

@@ -0,0 +1,5 @@
+/build
+/dist
+.eggs
+.cache
+*.egg-info*

@@ -35,3 +35,10 @@ set_target_properties(${BINARY_NAME}-pylib PROPERTIES COMPILE_DEFINITIONS "${OS_DEFINES};${FEATURE_DEFINES};${FUNCTION_DEFINES}")
 set(PYTHON_LIBRARY ${BINARY_NAME}-pylib PARENT_SCOPE)
 
 add_custom_target(${BINARY_NAME}-py ALL DEPENDS ${BINARY_NAME}-pylib ${CMAKE_CURRENT_BINARY_DIR}/build/lib/${BINARY_NAME}/__init__.py)
+
+file(GLOB TESTS ${CMAKE_CURRENT_SOURCE_DIR}/test_*.py)
+foreach(TEST IN LISTS TESTS)
+	string(REPLACE "${CMAKE_CURRENT_SOURCE_DIR}/test_" "" TEST_NAME "${TEST}")
+	string(REPLACE ".py" "" TEST_NAME "${TEST_NAME}")
+	add_test(python-${TEST_NAME} pytest ${TEST})
+endforeach()

@@ -12,8 +12,11 @@ bindir = os.environ.get("BINDIR", os.path.join(os.getcwd(), ".."))
 
 cpp = shlex.split(os.environ.get("CPP", "cc -E"))
 cppflags = shlex.split(os.environ.get("CPPFLAGS", ""))
+ldflags = shlex.split(os.environ.get("LDFLAGS", ""))
 if __name__ == "__main__":
     cppflags.extend(sys.argv[1:])
+if sys.platform == 'darwin':
+    ldflags.append('-Wl,-rpath,' + bindir)
 cppflags.extend(["-I" + incdir, "-I" + srcdir, "-I" + bindir])
 
 ffi.set_source("mgba._pylib", """
@@ -46,6 +49,7 @@ #include "platform/python/vfs-py.h"
 #undef PYEXPORT
 """, include_dirs=[incdir, srcdir],
      extra_compile_args=cppflags,
+     extra_link_args=ldflags,
      libraries=["mgba"],
      library_dirs=[bindir],
      sources=[os.path.join(pydir, path) for path in ["vfs-py.c", "core.c", "log.c", "sio.c"]])

@@ -0,0 +1,23 @@
+from PIL.ImageChops import difference
+from PIL.ImageOps import autocontrast
+from PIL.Image import open as PIOpen
+
+class VideoFrame(object):
+    def __init__(self, pilImage):
+        self.image = pilImage.convert('RGB')
+
+    @staticmethod
+    def diff(a, b):
+        diff = difference(a.image, b.image)
+        diffNormalized = autocontrast(diff)
+        return (VideoFrame(diff), VideoFrame(diffNormalized))
+
+    @staticmethod
+    def load(path):
+        with open(path, 'rb') as f:
+            image = PIOpen(f)
+            image.load()
+            return VideoFrame(image)
+
+    def save(self, path):
+        return self.image.save(path)

@@ -0,0 +1,47 @@
+from mgba.image import Image
+from collections import namedtuple
+from . import VideoFrame
+
+Output = namedtuple('Output', ['video'])
+
+class Tracer(object):
+    def __init__(self, core):
+        self.core = core
+        self.fb = Image(*core.desiredVideoDimensions())
+        self.core.setVideoBuffer(self.fb)
+        self._videoFifo = []
+
+    def yieldFrames(self, skip=0, limit=None):
+        self.core.reset()
+        skip = (skip or 0) + 1
+        while skip > 0:
+            frame = self.core.frameCounter
+            self.core.runFrame()
+            skip -= 1
+        while frame <= self.core.frameCounter and limit != 0:
+            self._videoFifo.append(VideoFrame(self.fb.toPIL()))
+            yield frame
+            frame = self.core.frameCounter
+            self.core.runFrame()
+            if limit is not None:
+                assert limit >= 0
+                limit -= 1
+
+    def video(self, generator=None, **kwargs):
+        if not generator:
+            generator = self.yieldFrames(**kwargs)
+        try:
+            while True:
+                if self._videoFifo:
+                    result = self._videoFifo[0]
+                    self._videoFifo = self._videoFifo[1:]
+                    yield result
+                else:
+                    next(generator)
+        except StopIteration:
+            return
+
+    def output(self, **kwargs):
+        generator = self.yieldFrames(**kwargs)
+
+        return mCoreOutput(video=self.video(generator=generator, **kwargs))

@@ -0,0 +1,96 @@
+import os, os.path
+import mgba.core, mgba.image
+import cinema.movie
+import itertools
+import glob
+import re
+import yaml
+from copy import deepcopy
+from cinema import VideoFrame
+from cinema.util import dictMerge
+
+class CinemaTest(object):
+    TEST = 'test.(mvl|gb|gba|nds)'
+
+    def __init__(self, path, root, settings={}):
+        self.fullPath = path or []
+        self.path = os.path.abspath(os.path.join(root, *self.fullPath))
+        self.root = root
+        self.name = '.'.join(path)
+        self.settings = settings
+        try:
+            with open(os.path.join(self.path, 'manifest.yml'), 'r') as f:
+                dictMerge(self.settings, yaml.safe_load(f))
+        except FileNotFoundError:
+            pass
+        self.tests = {}
+
+    def __repr__(self):
+        return '<%s %s>' % (self.__class__.__name__, self.name)
+
+    def setUp(self):
+        results = [f for f in glob.glob(os.path.join(self.path, 'test.*')) if re.search(self.TEST, f)]
+        self.core = mgba.core.loadPath(results[0])
+        if 'config' in self.settings:
+            self.config = mgba.core.Config(defaults=self.settings['config'])
+            self.core.loadConfig(self.config)
+            self.core.reset()
+
+    def addTest(self, name, cls=None, settings={}):
+        cls = cls or self.__class__
+        newSettings = deepcopy(self.settings)
+        dictMerge(newSettings, settings)
+        self.tests[name] = cls(self.fullPath + [name], self.root, newSettings)
+        return self.tests[name]
+
+    def outputSettings(self):
+        outputSettings = {}
+        if 'frames' in self.settings:
+            outputSettings['limit'] = self.settings['frames']
+        if 'skip' in self.settings:
+            outputSettings['skip'] = self.settings['skip']
+        return outputSettings
+
+    def __lt__(self, other):
+        return self.path < other.path
+
+class VideoTest(CinemaTest):
+    BASELINE = 'baseline_%04u.png'
+
+    def setUp(self):
+        super(VideoTest, self).setUp();
+        self.tracer = cinema.movie.Tracer(self.core)
+
+    def generateFrames(self):
+        for i, frame in zip(itertools.count(), self.tracer.video(**self.outputSettings())):
+            try:
+                baseline = VideoFrame.load(os.path.join(self.path, self.BASELINE % i))
+                yield baseline, frame, VideoFrame.diff(baseline, frame)
+            except FileNotFoundError:
+                yield None, frame, (None, None)
+
+    def test(self):
+        self.baseline, self.frames, self.diffs = zip(*self.generateFrames())
+        assert not any(any(diffs[0].image.convert("L").point(bool).getdata()) for diffs in self.diffs)
+
+    def generateBaseline(self):
+        for i, frame in zip(itertools.count(), self.tracer.video(**self.outputSettings())):
+            frame.save(os.path.join(self.path, self.BASELINE % i))
+
+def gatherTests(root=os.getcwd()):
+    tests = CinemaTest([], root)
+    for path, _, files in os.walk(root):
+        test = [f for f in files if re.match(CinemaTest.TEST, f)]
+        if not test:
+            continue
+        prefix = os.path.commonpath([path, root])
+        suffix = path[len(prefix)+1:]
+        testPath = suffix.split(os.sep)
+        testRoot = tests
+        for component in testPath[:-1]:
+            newTest = testRoot.tests.get(component)
+            if not newTest:
+                newTest = testRoot.addTest(component)
+            testRoot = newTest
+        testRoot.addTest(testPath[-1], VideoTest)
+    return tests

@@ -0,0 +1,9 @@
+def dictMerge(a, b):
+    for key, value in b.items():
+        if isinstance(value, dict):
+            if key in a:
+                dictMerge(a[key], value)
+            else:
+                a[key] = dict(value)
+        else:
+            a[key] = value

@@ -0,0 +1,49 @@
+import errno
+import itertools
+import os
+import os.path
+import pytest
+import yaml
+
+def pytest_addoption(parser):
+    parser.addoption("--rebaseline", action="store_true", help="output a new baseline instead of testing")
+    parser.addoption("--mark-failing", action="store_true", help="mark all failing tests as failing")
+    parser.addoption("--mark-succeeding", action="store_true", help="unmark all succeeding tests marked as failing")
+    parser.addoption("--output-diff", help="output diffs for failed tests to directory")
+
+EXPECTED = 'expected_%04u.png'
+RESULT = 'result_%04u.png'
+DIFF = 'diff_%04u.png'
+DIFF_NORM = 'diff_norm_%04u.png'
+
+def pytest_exception_interact(node, call, report):
+    outroot = node.config.getoption("--output-diff")
+    if report.failed and hasattr(node, 'funcargs'):
+        vtest = node.funcargs.get('vtest')
+        if outroot:
+            if not vtest:
+                return
+            outdir = os.path.join(outroot, *vtest.fullPath)
+            try:
+                os.makedirs(outdir)
+            except OSError as e:
+                if e.errno == errno.EEXIST and os.path.isdir(outdir):
+                    pass
+                else:
+                    raise
+            for i, expected, result, diff, diffNorm in zip(itertools.count(), vtest.baseline, vtest.frames, *zip(*vtest.diffs)):
+                result.save(os.path.join(outdir, RESULT % i))
+                if expected:
+                    expected.save(os.path.join(outdir, EXPECTED % i))
+                    diff.save(os.path.join(outdir, DIFF % i))
+                    diffNorm.save(os.path.join(outdir, DIFF_NORM % i))
+
+        if node.config.getoption("--mark-failing"):
+            try:
+                with open(os.path.join(vtest.path, 'manifest.yml'), 'r') as f:
+                    settings = yaml.safe_load(f)
+            except FileNotFoundError:
+                settings = {}
+            settings['fail'] = True
+            with open(os.path.join(vtest.path, 'manifest.yml'), 'w') as f:
+                yaml.dump(settings, f, default_flow_style=False)

@@ -0,0 +1,2 @@
+[aliases]
+test=pytest

@@ -1,6 +1,7 @@
 from setuptools import setup
 import re
 import os
+import sys
 
 os.environ["BINDIR"] = "${CMAKE_BINARY_DIR}"
 os.environ["CPPFLAGS"] = " ".join([d for d in "${INCLUDE_FLAGS}".split(";") if d])
@@ -21,9 +22,10 @@ author="Jeffrey Pfau",
       author_email="jeffrey@endrift.com",
       url="http://github.com/mgba-emu/mgba/",
       packages=["mgba"],
-      setup_requires=['cffi>=1.6'],
+      setup_requires=['cffi>=1.6', 'pytest-runner'],
       install_requires=['cffi>=1.6', 'cached-property'],
-      extras_require={'pil': ['Pillow>=2.3']},
+      extras_require={'pil': ['Pillow>=2.3'], 'cinema': ['pyyaml', 'pytest']},
+      tests_require=['mgba[cinema]', 'pytest'],
       cffi_modules=["_builder.py:ffi"],
       license="MPL 2.0",
       classifiers=classifiers

@@ -0,0 +1,61 @@
+import pytest
+import cinema.test
+import mgba.log
+import os.path
+import yaml
+
+mgba.log.installDefault(mgba.log.NullLogger())
+
+def flatten(d):
+    l = []
+    for k, v in d.tests.items():
+        if v.tests:
+            l.extend(flatten(v))
+        else:
+            l.append(v)
+    l.sort()
+    return l
+
+def pytest_generate_tests(metafunc):
+    if 'vtest' in metafunc.fixturenames:
+        tests = cinema.test.gatherTests(os.path.join(os.path.dirname(__file__), 'tests/cinema'))
+        testList = flatten(tests)
+        params = []
+        for test in testList:
+            marks = []
+            xfail = test.settings.get('fail')
+            if xfail:
+                marks = pytest.mark.xfail(reason=xfail if isinstance(xfail, str) else None)
+            params.append(pytest.param(test, id=test.name, marks=marks))
+        metafunc.parametrize('vtest', params, indirect=True)
+
+@pytest.fixture
+def vtest(request):
+    return request.param
+
+def test_video(vtest, pytestconfig):
+    vtest.setUp()
+    if pytestconfig.getoption('--rebaseline'):
+        vtest.generateBaseline()
+    else:
+        try:
+            vtest.test()
+        except FileNotFoundError:
+            raise
+        if pytestconfig.getoption('--mark-succeeding') and 'fail' in vtest.settings:
+            # TODO: This can fail if an entire directory is marked as failing
+            settings = {}
+            try:
+                with open(os.path.join(vtest.path, 'manifest.yml'), 'r') as f:
+                    settings = yaml.safe_load(f)
+            except FileNotFoundError:
+                pass
+            if 'fail' in settings:
+                del settings['fail']
+            else:
+                settings['fail'] = False
+            if settings:
+                with open(os.path.join(vtest.path, 'manifest.yml'), 'w') as f:
+                    yaml.dump(settings, f, default_flow_style=False)
+            else:
+                os.remove(os.path.join(vtest.path, 'manifest.yml'))

@@ -0,0 +1,19 @@
+Copyright (c) 2014-2017 Joonas Javanainen <joonas.javanainen@gmail.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

@@ -0,0 +1,206 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0150 _wait_ly_4
+00:0156 _wait_ly_5
+00:0180 test_finish
+00:01c4 wram_test
+00:01d3 hiram_test
+00:01d3 test_round1
+00:01d5 _wait_ly_6
+00:01db _wait_ly_7
+00:01f0 finish_round1
+00:01ff test_round2
+00:0201 _wait_ly_8
+00:0207 _wait_ly_9
+00:021d finish_round2
+00:c014 result_tmp
+00:c016 result_round1

@@ -0,0 +1,212 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:016f test_finish
+00:0183 _wait_ly_4
+00:0189 _wait_ly_5
+00:019f _print_results_halt_1
+00:01a2 _test_ok_cb_0
+00:01aa _print_sl_data55
+00:01b2 _print_sl_out55
+00:01b5 fail_1
+00:01c9 _wait_ly_6
+00:01cf _wait_ly_7
+00:01e5 _print_results_halt_2
+00:01e8 _test_failure_cb_0
+00:01f0 _print_sl_data56
+00:01fd _print_sl_out56
+00:0200 fail_0
+00:0214 _wait_ly_8
+00:021a _wait_ly_9
+00:0230 _print_results_halt_3
+00:0233 _test_failure_cb_1
+00:023b _print_sl_data57
+00:0248 _print_sl_out57

@@ -0,0 +1,192 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/reg_f.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0160 test_finish

@@ -0,0 +1,535 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/unused_hwio-GS.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c017 regs_save
+00:c017 regs_save.f
+00:c018 regs_save.a
+00:c019 regs_save.c
+00:c01a regs_save.b
+00:c01b regs_save.e
+00:c01c regs_save.d
+00:c01d regs_save.l
+00:c01e regs_save.h
+00:c01f regs_flags
+00:c020 regs_assert
+00:c020 regs_assert.f
+00:c021 regs_assert.a
+00:c022 regs_assert.c
+00:c023 regs_assert.b
+00:c024 regs_assert.e
+00:c025 regs_assert.d
+00:c026 regs_assert.l
+00:c027 regs_assert.h
+00:c028 memdump_len
+00:c029 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0161 _test_data_0
+00:0177 _finish_0
+00:0187 _test_data_1
+00:019d _finish_1
+00:01ad _test_data_2
+00:01c3 _finish_2
+00:01d3 _test_data_3
+00:01e9 _finish_3
+00:01f9 _test_data_4
+00:020f _finish_4
+00:021f _test_data_5
+00:0235 _finish_5
+00:0245 _test_data_6
+00:025b _finish_6
+00:026b _test_data_7
+00:0281 _finish_7
+00:0291 _test_data_8
+00:02a7 _finish_8
+00:02b7 _test_data_9
+00:02cd _finish_9
+00:02dd _test_data_10
+00:02f3 _finish_10
+00:0303 _test_data_11
+00:0319 _finish_11
+00:0329 _test_data_12
+00:033f _finish_12
+00:034f _test_data_13
+00:0365 _finish_13
+00:0375 _test_data_14
+00:038b _finish_14
+00:039b _test_data_15
+00:03b1 _finish_15
+00:03c1 _test_data_16
+00:03d7 _finish_16
+00:03e7 _test_data_17
+00:03fd _finish_17
+00:040d _test_data_18
+00:0423 _finish_18
+00:0433 _test_data_19
+00:0449 _finish_19
+00:0459 _test_data_20
+00:046f _finish_20
+00:047f _test_data_21
+00:0495 _finish_21
+00:04a5 _test_data_22
+00:04bb _finish_22
+00:04cb _test_data_23
+00:04e1 _finish_23
+00:04f1 _test_data_24
+00:0507 _finish_24
+00:0517 _test_data_25
+00:052d _finish_25
+00:053d _test_data_26
+00:0553 _finish_26
+00:0563 _test_data_27
+00:0579 _finish_27
+00:0589 _test_data_28
+00:059f _finish_28
+00:05af _test_data_29
+00:05c5 _finish_29
+00:05d5 _test_data_30
+00:05eb _finish_30
+00:05fb _test_data_31
+00:0611 _finish_31
+00:0621 _test_data_32
+00:0637 _finish_32
+00:0647 _test_data_33
+00:065d _finish_33
+00:066d _test_data_34
+00:0683 _finish_34
+00:0693 _test_data_35
+00:06a9 _finish_35
+00:06b9 _test_data_36
+00:06cf _finish_36
+00:06df _test_data_37
+00:06f5 _finish_37
+00:0705 _test_data_38
+00:071b _finish_38
+00:072b _test_data_39
+00:0741 _finish_39
+00:0751 _test_data_40
+00:0767 _finish_40
+00:0777 _test_data_41
+00:078d _finish_41
+00:079d _test_data_42
+00:07b3 _finish_42
+00:07c3 _test_data_43
+00:07d9 _finish_43
+00:07e9 _test_data_44
+00:07ff _finish_44
+00:080f _test_data_45
+00:0825 _finish_45
+00:0835 _test_data_46
+00:084b _finish_46
+00:085b _test_data_47
+00:0871 _finish_47
+00:0881 _test_data_48
+00:0897 _finish_48
+00:08a7 _test_data_49
+00:08bd _finish_49
+00:08cd _test_data_50
+00:08e3 _finish_50
+00:08f3 _test_data_51
+00:0909 _finish_51
+00:0919 _test_data_52
+00:092f _finish_52
+00:093f _test_data_53
+00:0955 _finish_53
+00:0965 _test_data_54
+00:097b _finish_54
+00:098b _test_data_55
+00:09a1 _finish_55
+00:09b1 _test_data_56
+00:09c7 _finish_56
+00:09d7 _test_data_57
+00:09ed _finish_57
+00:09fd _test_data_58
+00:0a13 _finish_58
+00:0a23 _test_data_59
+00:0a39 _finish_59
+00:0a49 _test_data_60
+00:0a5f _finish_60
+00:0a6f _test_data_61
+00:0a85 _finish_61
+00:0a95 _test_data_62
+00:0aab _finish_62
+00:0abb _test_data_63
+00:0ad1 _finish_63
+00:0ae1 _test_data_64
+00:0af7 _finish_64
+00:0b07 _test_data_65
+00:0b1d _finish_65
+00:0b2d _test_data_66
+00:0b43 _finish_66
+00:0b53 _test_data_67
+00:0b69 _finish_67
+00:0b79 _test_data_68
+00:0b8f _finish_68
+00:0b9f _test_data_69
+00:0bb5 _finish_69
+00:0bc5 _test_data_70
+00:0bdb _finish_70
+00:0beb _test_data_71
+00:0c01 _finish_71
+00:0c11 _test_data_72
+00:0c27 _finish_72
+00:0c37 _test_data_73
+00:0c4d _finish_73
+00:0c5d _test_data_74
+00:0c73 _finish_74
+00:0c83 _test_data_75
+00:0c99 _finish_75
+00:0ca9 _test_data_76
+00:0cbf _finish_76
+00:0ccf _test_data_77
+00:0ce5 _finish_77
+00:0cf5 _test_data_78
+00:0d0b _finish_78
+00:0d1b _test_data_79
+00:0d31 _finish_79
+00:0d41 _test_data_80
+00:0d57 _finish_80
+00:0d67 _test_data_81
+00:0d7d _finish_81
+00:0d8d _test_data_82
+00:0da3 _finish_82
+00:0db3 _test_data_83
+00:0dc9 _finish_83
+00:0dd9 _test_data_84
+00:0def _finish_84
+00:0dff _test_data_85
+00:0e15 _finish_85
+00:0e25 _test_data_86
+00:0e3b _finish_86
+00:0e4b _test_data_87
+00:0e61 _finish_87
+00:0e71 _test_data_88
+00:0e87 _finish_88
+00:0e97 _test_data_89
+00:0ead _finish_89
+00:0ebd _test_data_90
+00:0ed3 _finish_90
+00:0ee3 _test_data_91
+00:0ef9 _finish_91
+00:0f09 _test_data_92
+00:0f1f _finish_92
+00:0f2f _test_data_93
+00:0f45 _finish_93
+00:0f55 _test_data_94
+00:0f6b _finish_94
+00:0f7b _test_data_95
+00:0f91 _finish_95
+00:0fa1 _test_data_96
+00:0fb7 _finish_96
+00:0fc7 _test_data_97
+00:0fdd _finish_97
+00:0fed _test_data_98
+00:1003 _finish_98
+00:1013 _test_data_99
+00:1029 _finish_99
+00:1039 _test_data_100
+00:104f _finish_100
+00:105f _test_data_101
+00:1075 _finish_101
+00:1085 _test_data_102
+00:109b _finish_102
+00:10ab _test_data_103
+00:10c1 _finish_103
+00:10d1 _test_data_104
+00:10e7 _finish_104
+00:10f7 _test_data_105
+00:110d _finish_105
+00:111d _test_data_106
+00:1133 _finish_106
+00:1143 _test_data_107
+00:1159 _finish_107
+00:1169 _test_data_108
+00:117f _finish_108
+00:118f _test_data_109
+00:11a5 _finish_109
+00:11b5 _test_data_110
+00:11cb _finish_110
+00:11db _test_data_111
+00:11f1 _finish_111
+00:1201 _test_data_112
+00:1217 _finish_112
+00:1227 _test_data_113
+00:123d _finish_113
+00:124d _test_data_114
+00:1263 _finish_114
+00:1273 _test_data_115
+00:1289 _finish_115
+00:1299 _test_data_116
+00:12af _finish_116
+00:12bf _test_data_117
+00:12d5 _finish_117
+00:12e5 _test_data_118
+00:12fb _finish_118
+00:130b _test_data_119
+00:1321 _finish_119
+00:1331 _test_data_120
+00:1347 _finish_120
+00:1357 _test_data_121
+00:136d _finish_121
+00:137d _test_data_122
+00:1393 _finish_122
+00:13a3 _test_data_123
+00:13b9 _finish_123
+00:13c9 _test_data_124
+00:13df _finish_124
+00:13ef _test_data_125
+00:1405 _finish_125
+00:1415 _test_data_126
+00:142b _finish_126
+00:143b _test_data_127
+00:1451 _finish_127
+00:1461 _test_data_128
+00:1477 _finish_128
+00:1487 _test_data_129
+00:149d _finish_129
+00:14ad _test_data_130
+00:14c3 _finish_130
+00:14d3 _test_data_131
+00:14e9 _finish_131
+00:14f9 _test_data_132
+00:150f _finish_132
+00:151f _test_data_133
+00:1535 _finish_133
+00:1545 _test_data_134
+00:155b _finish_134
+00:156b _test_data_135
+00:1581 _finish_135
+00:1591 _test_data_136
+00:15a7 _finish_136
+00:15b7 _test_data_137
+00:15cd _finish_137
+00:15dd _test_data_138
+00:15f3 _finish_138
+00:1603 _test_data_139
+00:1619 _finish_139
+00:1629 _test_data_140
+00:163f _finish_140
+00:164f _test_data_141
+00:1665 _finish_141
+00:1675 _test_data_142
+00:168b _finish_142
+00:169b _test_data_143
+00:16b1 _finish_143
+00:16c1 _test_data_144
+00:16d7 _finish_144
+00:16e7 _test_data_145
+00:16fd _finish_145
+00:170d _test_data_146
+00:1723 _finish_146
+00:1733 _test_data_147
+00:1749 _finish_147
+00:1759 _test_data_148
+00:176f _finish_148
+00:177f _test_data_149
+00:1795 _finish_149
+00:17a5 _test_data_150
+00:17bb _finish_150
+00:17cb _test_data_151
+00:17e1 _finish_151
+00:17f1 _test_data_152
+00:1807 _finish_152
+00:1817 _test_data_153
+00:182d _finish_153
+00:1841 _wait_ly_4
+00:1847 _wait_ly_5
+00:185d _print_results_halt_1
+00:1860 _test_ok_cb_0
+00:1868 _print_sl_data55
+00:1870 _print_sl_out55
+00:1873 run_testcase
+00:189e _wait_ly_6
+00:18a4 _wait_ly_7
+00:18ba _print_results_halt_2
+00:18bd test_failure_cb
+00:18c5 _print_sl_data56
+00:18d1 _print_sl_out56
+00:18df _print_sl_data57
+00:18e3 _print_sl_out57
+00:18f1 _print_sl_data58
+00:1901 _print_sl_out58
+00:190f _print_sl_data59
+00:191c _print_sl_out59
+00:192d _print_sl_data60
+00:193a _print_sl_out60
+00:194b _print_sl_data61
+00:1958 _print_sl_out61
+00:195e fetch_test_data
+00:1978 print_got
+00:198a _print_zero
+00:198e _print_one
+00:1990 _print_bit
+00:1999 _skip
+00:199a _next
+00:c000 test_addr
+00:c002 test_got
+00:c003 test_reg
+00:c004 test_mask
+00:c005 test_str_write
+00:c00e test_str_expect

@@ -0,0 +1,1 @@
+config: {gb.model: SGB}

@@ -0,0 +1,212 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_ok_cb_0
+00:020d _print_sl_data55
+00:0215 _print_sl_out55
+00:0218 mismatch
+00:023b _wait_ly_6
+00:0241 _wait_ly_7
+00:0257 _print_results_halt_2
+00:025a mismatch_cb
+00:0262 _print_sl_data56
+00:0270 _print_sl_out56
+00:028a _print_sl_data57
+00:0294 _print_sl_out57
+00:02a5 _print_sl_data58
+00:02af _print_sl_out58
+00:02b8 hwio_data
+00:c014 mismatch_addr
+00:c016 mismatch_data
+00:c017 mismatch_mem

@@ -0,0 +1,1 @@
+fail: true

@@ -0,0 +1,212 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmg0.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_ok_cb_0
+00:020d _print_sl_data55
+00:0215 _print_sl_out55
+00:0218 mismatch
+00:023b _wait_ly_6
+00:0241 _wait_ly_7
+00:0257 _print_results_halt_2
+00:025a mismatch_cb
+00:0262 _print_sl_data56
+00:0270 _print_sl_out56
+00:028a _print_sl_data57
+00:0294 _print_sl_out57
+00:02a5 _print_sl_data58
+00:02af _print_sl_out58
+00:02b8 hwio_data
+00:c014 mismatch_addr
+00:c016 mismatch_data
+00:c017 mismatch_mem

@@ -0,0 +1,212 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCXmgb.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_ok_cb_0
+00:020d _print_sl_data55
+00:0215 _print_sl_out55
+00:0218 mismatch
+00:023b _wait_ly_6
+00:0241 _wait_ly_7
+00:0257 _print_results_halt_2
+00:025a mismatch_cb
+00:0262 _print_sl_data56
+00:0270 _print_sl_out56
+00:028a _print_sl_data57
+00:0294 _print_sl_out57
+00:02a5 _print_sl_data58
+00:02af _print_sl_out58
+00:02b8 hwio_data
+00:c014 mismatch_addr
+00:c016 mismatch_data
+00:c017 mismatch_mem

@@ -0,0 +1,198 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg.gb".
+
+[labels]
+0001:4bf2 print_load_font
+0001:4bff print_string
+0001:4c09 print_a
+0001:4c13 print_newline
+0001:4c1e print_digit
+0001:4c2b print_regs
+0001:4c34 _print_sl_data0
+0001:4c3a _print_sl_out0
+0001:4c47 _print_sl_data1
+0001:4c4d _print_sl_out1
+0001:4c5f _print_sl_data2
+0001:4c65 _print_sl_out2
+0001:4c72 _print_sl_data3
+0001:4c78 _print_sl_out3
+0001:4c8a _print_sl_data4
+0001:4c90 _print_sl_out4
+0001:4c9d _print_sl_data5
+0001:4ca3 _print_sl_out5
+0001:4cb5 _print_sl_data6
+0001:4cbb _print_sl_out6
+0001:4cc8 _print_sl_data7
+0001:4cce _print_sl_out7
+0001:4000 font
+0000:c000 regs_save
+0000:c000 regs_save.f
+0000:c001 regs_save.a
+0000:c002 regs_save.c
+0000:c003 regs_save.b
+0000:c004 regs_save.e
+0000:c005 regs_save.d
+0000:c006 regs_save.l
+0000:c007 regs_save.h
+0000:c008 regs_flags
+0000:c009 regs_assert
+0000:c009 regs_assert.f
+0000:c00a regs_assert.a
+0000:c00b regs_assert.c
+0000:c00c regs_assert.b
+0000:c00d regs_assert.e
+0000:c00e regs_assert.d
+0000:c00f regs_assert.l
+0000:c010 regs_assert.h
+0000:c011 memdump_len
+0000:c012 memdump_addr
+0001:47f0 memcpy
+0001:47f9 memset
+0001:4802 clear_vram
+0001:480d reset_screen
+0001:481a process_results
+0001:481f _wait_ly_0
+0001:4825 _wait_ly_1
+0001:4841 _wait_ly_2
+0001:4847 _wait_ly_3
+0001:4860 _process_results_cb
+0001:486b _print_sl_data8
+0001:4875 _print_sl_out8
+0001:488f _print_sl_data9
+0001:489a _print_sl_out9
+0001:48b2 _print_sl_data10
+0001:48be _print_sl_out10
+0001:48bf dump_mem
+0001:48cf _wait_ly_4
+0001:48d5 _wait_ly_5
+0001:48f1 _dump_mem_line
+0001:491b _check_asserts
+0001:4929 _print_sl_data11
+0001:492c _print_sl_out11
+0001:4938 _print_sl_data12
+0001:493a _print_sl_out12
+0001:4942 _print_sl_data13
+0001:4945 _print_sl_out13
+0001:494f __check_assert_fail0
+0001:495a _print_sl_data14
+0001:495d _print_sl_out14
+0001:4960 __check_assert_ok0
+0001:4968 _print_sl_data15
+0001:496d _print_sl_out15
+0001:496f __check_assert_skip0
+0001:4977 _print_sl_data16
+0001:497f _print_sl_out16
+0001:497f __check_assert_out0
+0001:498b _print_sl_data17
+0001:498d _print_sl_out17
+0001:4995 _print_sl_data18
+0001:4998 _print_sl_out18
+0001:49a2 __check_assert_fail1
+0001:49ad _print_sl_data19
+0001:49b0 _print_sl_out19
+0001:49b3 __check_assert_ok1
+0001:49bb _print_sl_data20
+0001:49c0 _print_sl_out20
+0001:49c2 __check_assert_skip1
+0001:49ca _print_sl_data21
+0001:49d2 _print_sl_out21
+0001:49d2 __check_assert_out1
+0001:49dd _print_sl_data22
+0001:49e0 _print_sl_out22
+0001:49ec _print_sl_data23
+0001:49ee _print_sl_out23
+0001:49f6 _print_sl_data24
+0001:49f9 _print_sl_out24
+0001:4a03 __check_assert_fail2
+0001:4a0e _print_sl_data25
+0001:4a11 _print_sl_out25
+0001:4a14 __check_assert_ok2
+0001:4a1c _print_sl_data26
+0001:4a21 _print_sl_out26
+0001:4a23 __check_assert_skip2
+0001:4a2b _print_sl_data27
+0001:4a33 _print_sl_out27
+0001:4a33 __check_assert_out2
+0001:4a3f _print_sl_data28
+0001:4a41 _print_sl_out28
+0001:4a49 _print_sl_data29
+0001:4a4c _print_sl_out29
+0001:4a56 __check_assert_fail3
+0001:4a61 _print_sl_data30
+0001:4a64 _print_sl_out30
+0001:4a67 __check_assert_ok3
+0001:4a6f _print_sl_data31
+0001:4a74 _print_sl_out31
+0001:4a76 __check_assert_skip3
+0001:4a7e _print_sl_data32
+0001:4a86 _print_sl_out32
+0001:4a86 __check_assert_out3
+0001:4a91 _print_sl_data33
+0001:4a94 _print_sl_out33
+0001:4aa0 _print_sl_data34
+0001:4aa2 _print_sl_out34
+0001:4aaa _print_sl_data35
+0001:4aad _print_sl_out35
+0001:4ab7 __check_assert_fail4
+0001:4ac2 _print_sl_data36
+0001:4ac5 _print_sl_out36
+0001:4ac8 __check_assert_ok4
+0001:4ad0 _print_sl_data37
+0001:4ad5 _print_sl_out37
+0001:4ad7 __check_assert_skip4
+0001:4adf _print_sl_data38
+0001:4ae7 _print_sl_out38
+0001:4ae7 __check_assert_out4
+0001:4af3 _print_sl_data39
+0001:4af5 _print_sl_out39
+0001:4afd _print_sl_data40
+0001:4b00 _print_sl_out40
+0001:4b0a __check_assert_fail5
+0001:4b15 _print_sl_data41
+0001:4b18 _print_sl_out41
+0001:4b1b __check_assert_ok5
+0001:4b23 _print_sl_data42
+0001:4b28 _print_sl_out42
+0001:4b2a __check_assert_skip5
+0001:4b32 _print_sl_data43
+0001:4b3a _print_sl_out43
+0001:4b3a __check_assert_out5
+0001:4b45 _print_sl_data44
+0001:4b48 _print_sl_out44
+0001:4b54 _print_sl_data45
+0001:4b56 _print_sl_out45
+0001:4b5e _print_sl_data46
+0001:4b61 _print_sl_out46
+0001:4b6b __check_assert_fail6
+0001:4b76 _print_sl_data47
+0001:4b79 _print_sl_out47
+0001:4b7c __check_assert_ok6
+0001:4b84 _print_sl_data48
+0001:4b89 _print_sl_out48
+0001:4b8b __check_assert_skip6
+0001:4b93 _print_sl_data49
+0001:4b9b _print_sl_out49
+0001:4b9b __check_assert_out6
+0001:4ba7 _print_sl_data50
+0001:4ba9 _print_sl_out50
+0001:4bb1 _print_sl_data51
+0001:4bb4 _print_sl_out51
+0001:4bbe __check_assert_fail7
+0001:4bc9 _print_sl_data52
+0001:4bcc _print_sl_out52
+0001:4bcf __check_assert_ok7
+0001:4bd7 _print_sl_data53
+0001:4bdc _print_sl_out53
+0001:4bde __check_assert_skip7
+0001:4be6 _print_sl_data54
+0001:4bee _print_sl_out54
+0001:4bee __check_assert_out7
+0000:01d2 invalid_sp
+0000:01d7 _wait_ly_6
+0000:01dd _wait_ly_7
+0000:01f9 _wait_ly_8
+0000:01ff _wait_ly_9
+0000:0218 _test_failure_cb_0
+0000:0220 _print_sl_data55
+0000:0231 _print_sl_out55
+0000:c014 sp_save

@@ -0,0 +1,1 @@
+fail: true

@@ -0,0 +1,199 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01d2 invalid_sp
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_failure_cb_0
+00:020d _print_sl_data55
+00:021e _print_sl_out55
+00:c014 sp_save

@@ -0,0 +1,199 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABCX.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01d2 invalid_sp
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_failure_cb_0
+00:020d _print_sl_data55
+00:021e _print_sl_out55
+00:c014 sp_save

@@ -0,0 +1,1 @@
+config: {gb.model: MGB}

@@ -0,0 +1,199 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01d2 invalid_sp
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_failure_cb_0
+00:020d _print_sl_data55
+00:021e _print_sl_out55
+00:c014 sp_save

@@ -0,0 +1,1 @@
+config: {gb.model: SGB}

@@ -0,0 +1,199 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01d2 invalid_sp
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_failure_cb_0
+00:020d _print_sl_data55
+00:021e _print_sl_out55
+00:c014 sp_save

@@ -0,0 +1,1 @@
+config: {gb.model: SGB2}

@@ -0,0 +1,199 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb2.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:01d2 invalid_sp
+00:01e6 _wait_ly_4
+00:01ec _wait_ly_5
+00:0202 _print_results_halt_1
+00:0205 _test_failure_cb_0
+00:020d _print_sl_data55
+00:021e _print_sl_out55
+00:c014 sp_save

@@ -0,0 +1,223 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:0184 test_finish
+00:0198 _wait_ly_6
+00:019e _wait_ly_7
+00:01b4 _print_results_halt_1
+00:01b7 _test_ok_cb_0
+00:01bf _print_sl_data55
+00:01c7 _print_sl_out55
+00:01ca wram_test
+00:01cd fail_round1
+00:01e1 _wait_ly_8
+00:01e7 _wait_ly_9
+00:01fd _print_results_halt_2
+00:0200 _test_failure_cb_0
+00:0208 _print_sl_data56
+00:0216 _print_sl_out56
+00:0219 fail_round2
+00:022d _wait_ly_10
+00:0233 _wait_ly_11
+00:0249 _print_results_halt_3
+00:024c _test_failure_cb_1
+00:0254 _print_sl_data57
+00:0262 _print_sl_out57
+00:1f80 hiram_test
+00:1f87 _wait_ly_12
+00:1f8d _wait_ly_13
+00:1fa1 test_round2
+00:1fa8 _wait_ly_14
+00:1fae _wait_ly_15
+00:1fca finish_round1
+00:1ada finish_round2

@@ -0,0 +1,204 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:0177 test_finish
+00:01cf hiram_test
+00:01d2 _wait_ly_6
+00:01d8 _wait_ly_7
+00:01ec finish_round1
+00:01ed _wait_ly_8
+00:01f3 _wait_ly_9
+00:0208 finish_round2
+00:0209 _wait_ly_10
+00:020f _wait_ly_11
+00:0225 finish_round3

@@ -0,0 +1,223 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:0184 test_finish
+00:0198 _wait_ly_6
+00:019e _wait_ly_7
+00:01b4 _print_results_halt_1
+00:01b7 _test_ok_cb_0
+00:01bf _print_sl_data55
+00:01c7 _print_sl_out55
+00:01ca wram_test
+00:01cd fail_round1
+00:01e1 _wait_ly_8
+00:01e7 _wait_ly_9
+00:01fd _print_results_halt_2
+00:0200 _test_failure_cb_0
+00:0208 _print_sl_data56
+00:0216 _print_sl_out56
+00:0219 fail_round2
+00:022d _wait_ly_10
+00:0233 _wait_ly_11
+00:0249 _print_results_halt_3
+00:024c _test_failure_cb_1
+00:0254 _print_sl_data57
+00:0262 _print_sl_out57
+00:1f80 hiram_test
+00:1f87 _wait_ly_12
+00:1f8d _wait_ly_13
+00:1fa1 test_round2
+00:1fa8 _wait_ly_14
+00:1fae _wait_ly_15
+00:1fca finish_round1
+00:1ada finish_round2

@@ -0,0 +1,204 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing2.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:0177 test_finish
+00:01cf hiram_test
+00:01d2 _wait_ly_6
+00:01d8 _wait_ly_7
+00:01ec finish_round1
+00:01ed _wait_ly_8
+00:01f3 _wait_ly_9
+00:0208 finish_round2
+00:0209 _wait_ly_10
+00:020f _wait_ly_11
+00:0225 finish_round3

@@ -0,0 +1,228 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/di_timing-GS.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0158 _wait_ly_4
+00:015e _wait_ly_5
+00:016d test_round1
+00:0177 _delay_long_time_0
+00:0186 finish_round1
+00:0189 _wait_ly_6
+00:018f _wait_ly_7
+00:019e test_round2
+00:01a8 _delay_long_time_1
+00:01b4 test_finish
+00:01c8 _wait_ly_8
+00:01ce _wait_ly_9
+00:01e4 _print_results_halt_1
+00:01e7 _test_ok_cb_0
+00:01ef _print_sl_data55
+00:01f7 _print_sl_out55
+00:01fa fail_halt
+00:020e _wait_ly_10
+00:0214 _wait_ly_11
+00:022a _print_results_halt_2
+00:022d _test_failure_cb_0
+00:0235 _print_sl_data56
+00:0240 _print_sl_out56
+00:0243 fail_round1
+00:0257 _wait_ly_12
+00:025d _wait_ly_13
+00:0273 _print_results_halt_3
+00:0276 _test_failure_cb_1
+00:027e _print_sl_data57
+00:028c _print_sl_out57
+00:028f fail_round2
+00:02a3 _wait_ly_14
+00:02a9 _wait_ly_15
+00:02bf _print_results_halt_4
+00:02c2 _test_failure_cb_2
+00:02ca _print_sl_data58
+00:02d8 _print_sl_out58

@@ -0,0 +1,192 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/div_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0232 test_finish

@@ -0,0 +1,192 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0160 test_finish

@@ -0,0 +1,1 @@
+fail: true

@@ -0,0 +1,219 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/hblank_ly_scx_timing-GS.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:03a2 _wait_ly_6
+00:03a8 _wait_ly_7
+00:03be _print_results_halt_1
+00:03c1 _test_ok_cb_0
+00:03c9 _print_sl_data55
+00:03d1 _print_sl_out55
+00:03d4 test_fail
+00:0404 _wait_ly_8
+00:040a _wait_ly_9
+00:0420 _print_results_halt_2
+00:0423 _test_failure_dump_cb_0
+00:042e _print_sl_data56
+00:0438 _print_sl_out56
+00:044c _print_sl_data57
+00:0458 _print_sl_out57
+00:045b standard_delay
+00:0473 setup_and_wait
+00:0473 _wait_ly_10
+00:0479 _wait_ly_11
+00:048d fail_halt
+00:04a1 _wait_ly_12
+00:04a7 _wait_ly_13
+00:04bd _print_results_halt_3
+00:04c0 _test_failure_cb_0
+00:04c8 _print_sl_data58
+00:04d3 _print_sl_out58

@@ -0,0 +1,203 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_1_2_timing-GS.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:01ab setup_and_wait_mode1
+00:01ab _wait_ly_6
+00:01be setup_and_wait_mode2
+00:01cb fail_halt
+00:01df _wait_ly_7
+00:01e5 _wait_ly_8
+00:01fb _print_results_halt_1
+00:01fe _test_failure_cb_0
+00:0206 _print_sl_data55
+00:0211 _print_sl_out55

@@ -0,0 +1,203 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_0_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:01a9 setup_and_wait_mode2
+00:01a9 _wait_ly_6
+00:01cc setup_and_wait_mode0
+00:01d9 fail_halt
+00:01ed _wait_ly_7
+00:01f3 _wait_ly_8
+00:0209 _print_results_halt_1
+00:020c _test_failure_cb_0
+00:0214 _print_sl_data55
+00:021f _print_sl_out55

@@ -0,0 +1,202 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:0207 setup_and_wait_mode2
+00:0207 _wait_ly_6
+00:022a fail_halt
+00:023e _wait_ly_7
+00:0244 _wait_ly_8
+00:025a _print_results_halt_1
+00:025d _test_failure_cb_0
+00:0265 _print_sl_data55
+00:0270 _print_sl_out55

@@ -0,0 +1,437 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing_sprites.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c0c2 regs_save
+00:c0c2 regs_save.f
+00:c0c3 regs_save.a
+00:c0c4 regs_save.c
+00:c0c5 regs_save.b
+00:c0c6 regs_save.e
+00:c0c7 regs_save.d
+00:c0c8 regs_save.l
+00:c0c9 regs_save.h
+00:c0ca regs_flags
+00:c0cb regs_assert
+00:c0cb regs_assert.f
+00:c0cc regs_assert.a
+00:c0cd regs_assert.c
+00:c0ce regs_assert.b
+00:c0cf regs_assert.e
+00:c0d0 regs_assert.d
+00:c0d1 regs_assert.l
+00:c0d2 regs_assert.h
+00:c0d3 memdump_len
+00:c0d4 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0174 _testcase_data_0
+00:0176 _testcase_end_0
+00:0187 _testcase_data_1
+00:018a _testcase_end_1
+00:019b _testcase_data_2
+00:019f _testcase_end_2
+00:01b0 _testcase_data_3
+00:01b5 _testcase_end_3
+00:01c6 _testcase_data_4
+00:01cc _testcase_end_4
+00:01dd _testcase_data_5
+00:01e4 _testcase_end_5
+00:01f5 _testcase_data_6
+00:01fd _testcase_end_6
+00:020e _testcase_data_7
+00:0217 _testcase_end_7
+00:0228 _testcase_data_8
+00:0232 _testcase_end_8
+00:0243 _testcase_data_9
+00:024e _testcase_end_9
+00:025f _testcase_data_10
+00:026a _testcase_end_10
+00:027b _testcase_data_11
+00:0286 _testcase_end_11
+00:0297 _testcase_data_12
+00:02a2 _testcase_end_12
+00:02b3 _testcase_data_13
+00:02be _testcase_end_13
+00:02cf _testcase_data_14
+00:02da _testcase_end_14
+00:02eb _testcase_data_15
+00:02f6 _testcase_end_15
+00:0307 _testcase_data_16
+00:0312 _testcase_end_16
+00:0323 _testcase_data_17
+00:032e _testcase_end_17
+00:033f _testcase_data_18
+00:034a _testcase_end_18
+00:035b _testcase_data_19
+00:0366 _testcase_end_19
+00:0377 _testcase_data_20
+00:0382 _testcase_end_20
+00:0393 _testcase_data_21
+00:039e _testcase_end_21
+00:03af _testcase_data_22
+00:03ba _testcase_end_22
+00:03cb _testcase_data_23
+00:03d6 _testcase_end_23
+00:03e7 _testcase_data_24
+00:03f2 _testcase_end_24
+00:0403 _testcase_data_25
+00:040e _testcase_end_25
+00:041f _testcase_data_26
+00:042a _testcase_end_26
+00:043b _testcase_data_27
+00:0446 _testcase_end_27
+00:0457 _testcase_data_28
+00:0462 _testcase_end_28
+00:0473 _testcase_data_29
+00:047e _testcase_end_29
+00:048f _testcase_data_30
+00:049a _testcase_end_30
+00:04ab _testcase_data_31
+00:04b6 _testcase_end_31
+00:04c7 _testcase_data_32
+00:04d2 _testcase_end_32
+00:04e3 _testcase_data_33
+00:04ee _testcase_end_33
+00:04ff _testcase_data_34
+00:050a _testcase_end_34
+00:051b _testcase_data_35
+00:0526 _testcase_end_35
+00:0537 _testcase_data_36
+00:0542 _testcase_end_36
+00:0553 _testcase_data_37
+00:055e _testcase_end_37
+00:056f _testcase_data_38
+00:057a _testcase_end_38
+00:058b _testcase_data_39
+00:0596 _testcase_end_39
+00:05a7 _testcase_data_40
+00:05b2 _testcase_end_40
+00:05c3 _testcase_data_41
+00:05ce _testcase_end_41
+00:05df _testcase_data_42
+00:05ea _testcase_end_42
+00:05fb _testcase_data_43
+00:0606 _testcase_end_43
+00:0617 _testcase_data_44
+00:0622 _testcase_end_44
+00:0633 _testcase_data_45
+00:063e _testcase_end_45
+00:064f _testcase_data_46
+00:065a _testcase_end_46
+00:066b _testcase_data_47
+00:0676 _testcase_end_47
+00:0687 _testcase_data_48
+00:0692 _testcase_end_48
+00:06a3 _testcase_data_49
+00:06ae _testcase_end_49
+00:06bf _testcase_data_50
+00:06ca _testcase_end_50
+00:06db _testcase_data_51
+00:06e6 _testcase_end_51
+00:06f7 _testcase_data_52
+00:06f9 _testcase_end_52
+00:070a _testcase_data_53
+00:070c _testcase_end_53
+00:071d _testcase_data_54
+00:071f _testcase_end_54
+00:0730 _testcase_data_55
+00:0732 _testcase_end_55
+00:0743 _testcase_data_56
+00:0745 _testcase_end_56
+00:0756 _testcase_data_57
+00:0758 _testcase_end_57
+00:0769 _testcase_data_58
+00:076b _testcase_end_58
+00:077c _testcase_data_59
+00:077e _testcase_end_59
+00:078f _testcase_data_60
+00:0791 _testcase_end_60
+00:07a2 _testcase_data_61
+00:07a4 _testcase_end_61
+00:07b5 _testcase_data_62
+00:07b7 _testcase_end_62
+00:07c8 _testcase_data_63
+00:07ca _testcase_end_63
+00:07db _testcase_data_64
+00:07dd _testcase_end_64
+00:07ee _testcase_data_65
+00:07f0 _testcase_end_65
+00:0801 _testcase_data_66
+00:0803 _testcase_end_66
+00:0814 _testcase_data_67
+00:0816 _testcase_end_67
+00:0827 _testcase_data_68
+00:0829 _testcase_end_68
+00:083a _testcase_data_69
+00:083c _testcase_end_69
+00:084d _testcase_data_70
+00:084f _testcase_end_70
+00:0860 _testcase_data_71
+00:0862 _testcase_end_71
+00:0873 _testcase_data_72
+00:0875 _testcase_end_72
+00:0886 _testcase_data_73
+00:0888 _testcase_end_73
+00:0899 _testcase_data_74
+00:089b _testcase_end_74
+00:08ac _testcase_data_75
+00:08ae _testcase_end_75
+00:08bf _testcase_data_76
+00:08c1 _testcase_end_76
+00:08d2 _testcase_data_77
+00:08d4 _testcase_end_77
+00:08e5 _testcase_data_78
+00:08e8 _testcase_end_78
+00:08f9 _testcase_data_79
+00:08fc _testcase_end_79
+00:090d _testcase_data_80
+00:0910 _testcase_end_80
+00:0921 _testcase_data_81
+00:0924 _testcase_end_81
+00:0935 _testcase_data_82
+00:0938 _testcase_end_82
+00:0949 _testcase_data_83
+00:094c _testcase_end_83
+00:095d _testcase_data_84
+00:0960 _testcase_end_84
+00:0971 _testcase_data_85
+00:0974 _testcase_end_85
+00:0985 _testcase_data_86
+00:0988 _testcase_end_86
+00:0999 _testcase_data_87
+00:099c _testcase_end_87
+00:09ad _testcase_data_88
+00:09b0 _testcase_end_88
+00:09c1 _testcase_data_89
+00:09c4 _testcase_end_89
+00:09d5 _testcase_data_90
+00:09d8 _testcase_end_90
+00:09e9 _testcase_data_91
+00:09ec _testcase_end_91
+00:09fd _testcase_data_92
+00:0a00 _testcase_end_92
+00:0a11 _testcase_data_93
+00:0a14 _testcase_end_93
+00:0a25 _testcase_data_94
+00:0a28 _testcase_end_94
+00:0a39 _testcase_data_95
+00:0a44 _testcase_end_95
+00:0a55 _testcase_data_96
+00:0a60 _testcase_end_96
+00:0a71 _testcase_data_97
+00:0a7c _testcase_end_97
+00:0a8d _testcase_data_98
+00:0a98 _testcase_end_98
+00:0aa9 _testcase_data_99
+00:0ab4 _testcase_end_99
+00:0ac5 _testcase_data_100
+00:0ad0 _testcase_end_100
+00:0ae1 _testcase_data_101
+00:0aec _testcase_end_101
+00:0afd _testcase_data_102
+00:0b08 _testcase_end_102
+00:0b19 _testcase_data_103
+00:0b24 _testcase_end_103
+00:0b35 _testcase_data_104
+00:0b40 _testcase_end_104
+00:0b54 _wait_ly_4
+00:0b5a _wait_ly_5
+00:0b70 _print_results_halt_1
+00:0b73 _test_ok_cb_0
+00:0b7b _print_sl_data55
+00:0b83 _print_sl_out55
+00:0b86 run_testcase
+00:0b88 _wait_ly_6
+00:0b8e _wait_ly_7
+00:0bb9 testcase_round_a
+00:0bc4 testcase_round_a_ret
+00:0bd4 testcase_round_b
+00:0bdf testcase_round_b_ret
+00:0bf0 prepare_sprites
+00:0c06 prepare_nop_area
+00:0c0f setup_and_wait_mode2
+00:0c0f _wait_ly_8
+00:0c32 test_fail
+00:0c46 _wait_ly_9
+00:0c4c _wait_ly_10
+00:0c62 _print_results_halt_2
+00:0c65 _test_fail_cb
+00:0c6d _print_sl_data56
+00:0c74 _print_sl_out56
+00:0c82 _print_sl_data57
+00:0c8a _print_sl_out57
+00:0c8d fail_halt
+00:0ca1 _wait_ly_11
+00:0ca7 _wait_ly_12
+00:0cbd _print_results_halt_3
+00:0cc0 _test_failure_cb_0
+00:0cc8 _print_sl_data58
+00:0cd3 _print_sl_out58
+00:c000 testcase_id
+00:c002 nop_area_a
+00:c062 nop_area_b

@@ -0,0 +1,202 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode3_timing.gb".
+
+[labels]
+01:4bff print_load_font
+01:4c0c print_string
+01:4c16 print_a
+01:4c20 print_newline
+01:4c2b print_digit
+01:4c38 print_regs
+01:4c41 _print_sl_data0
+01:4c47 _print_sl_out0
+01:4c54 _print_sl_data1
+01:4c5a _print_sl_out1
+01:4c6c _print_sl_data2
+01:4c72 _print_sl_out2
+01:4c7f _print_sl_data3
+01:4c85 _print_sl_out3
+01:4c97 _print_sl_data4
+01:4c9d _print_sl_out4
+01:4caa _print_sl_data5
+01:4cb0 _print_sl_out5
+01:4cc2 _print_sl_data6
+01:4cc8 _print_sl_out6
+01:4cd5 _print_sl_data7
+01:4cdb _print_sl_out7
+01:4000 font
+00:c000 regs_save
+00:c000 regs_save.f
+00:c001 regs_save.a
+00:c002 regs_save.c
+00:c003 regs_save.b
+00:c004 regs_save.e
+00:c005 regs_save.d
+00:c006 regs_save.l
+00:c007 regs_save.h
+00:c008 regs_flags
+00:c009 regs_assert
+00:c009 regs_assert.f
+00:c00a regs_assert.a
+00:c00b regs_assert.c
+00:c00c regs_assert.b
+00:c00d regs_assert.e
+00:c00e regs_assert.d
+00:c00f regs_assert.l
+00:c010 regs_assert.h
+00:c011 memdump_len
+00:c012 memdump_addr
+01:47f0 memcpy
+01:47f9 memset
+01:4802 memcmp
+01:4810 clear_vram
+01:481a clear_oam
+01:4824 disable_lcd_safe
+01:482a _wait_ly_0
+01:4830 _wait_ly_1
+01:4839 reset_screen
+01:484d process_results
+01:4861 _wait_ly_2
+01:4867 _wait_ly_3
+01:487d _print_results_halt_0
+01:4880 _process_results_cb
+01:488b _print_sl_data8
+01:4895 _print_sl_out8
+01:48af _print_sl_data9
+01:48ba _print_sl_out9
+01:48d2 _print_sl_data10
+01:48de _print_sl_out10
+01:48df dump_mem
+01:48fe _dump_mem_line
+01:4928 _check_asserts
+01:4936 _print_sl_data11
+01:4939 _print_sl_out11
+01:4945 _print_sl_data12
+01:4947 _print_sl_out12
+01:494f _print_sl_data13
+01:4952 _print_sl_out13
+01:495c __check_assert_fail0
+01:4967 _print_sl_data14
+01:496a _print_sl_out14
+01:496d __check_assert_ok0
+01:4975 _print_sl_data15
+01:497a _print_sl_out15
+01:497c __check_assert_skip0
+01:4984 _print_sl_data16
+01:498c _print_sl_out16
+01:498c __check_assert_out0
+01:4998 _print_sl_data17
+01:499a _print_sl_out17
+01:49a2 _print_sl_data18
+01:49a5 _print_sl_out18
+01:49af __check_assert_fail1
+01:49ba _print_sl_data19
+01:49bd _print_sl_out19
+01:49c0 __check_assert_ok1
+01:49c8 _print_sl_data20
+01:49cd _print_sl_out20
+01:49cf __check_assert_skip1
+01:49d7 _print_sl_data21
+01:49df _print_sl_out21
+01:49df __check_assert_out1
+01:49ea _print_sl_data22
+01:49ed _print_sl_out22
+01:49f9 _print_sl_data23
+01:49fb _print_sl_out23
+01:4a03 _print_sl_data24
+01:4a06 _print_sl_out24
+01:4a10 __check_assert_fail2
+01:4a1b _print_sl_data25
+01:4a1e _print_sl_out25
+01:4a21 __check_assert_ok2
+01:4a29 _print_sl_data26
+01:4a2e _print_sl_out26
+01:4a30 __check_assert_skip2
+01:4a38 _print_sl_data27
+01:4a40 _print_sl_out27
+01:4a40 __check_assert_out2
+01:4a4c _print_sl_data28
+01:4a4e _print_sl_out28
+01:4a56 _print_sl_data29
+01:4a59 _print_sl_out29
+01:4a63 __check_assert_fail3
+01:4a6e _print_sl_data30
+01:4a71 _print_sl_out30
+01:4a74 __check_assert_ok3
+01:4a7c _print_sl_data31
+01:4a81 _print_sl_out31
+01:4a83 __check_assert_skip3
+01:4a8b _print_sl_data32
+01:4a93 _print_sl_out32
+01:4a93 __check_assert_out3
+01:4a9e _print_sl_data33
+01:4aa1 _print_sl_out33
+01:4aad _print_sl_data34
+01:4aaf _print_sl_out34
+01:4ab7 _print_sl_data35
+01:4aba _print_sl_out35
+01:4ac4 __check_assert_fail4
+01:4acf _print_sl_data36
+01:4ad2 _print_sl_out36
+01:4ad5 __check_assert_ok4
+01:4add _print_sl_data37
+01:4ae2 _print_sl_out37
+01:4ae4 __check_assert_skip4
+01:4aec _print_sl_data38
+01:4af4 _print_sl_out38
+01:4af4 __check_assert_out4
+01:4b00 _print_sl_data39
+01:4b02 _print_sl_out39
+01:4b0a _print_sl_data40
+01:4b0d _print_sl_out40
+01:4b17 __check_assert_fail5
+01:4b22 _print_sl_data41
+01:4b25 _print_sl_out41
+01:4b28 __check_assert_ok5
+01:4b30 _print_sl_data42
+01:4b35 _print_sl_out42
+01:4b37 __check_assert_skip5
+01:4b3f _print_sl_data43
+01:4b47 _print_sl_out43
+01:4b47 __check_assert_out5
+01:4b52 _print_sl_data44
+01:4b55 _print_sl_out44
+01:4b61 _print_sl_data45
+01:4b63 _print_sl_out45
+01:4b6b _print_sl_data46
+01:4b6e _print_sl_out46
+01:4b78 __check_assert_fail6
+01:4b83 _print_sl_data47
+01:4b86 _print_sl_out47
+01:4b89 __check_assert_ok6
+01:4b91 _print_sl_data48
+01:4b96 _print_sl_out48
+01:4b98 __check_assert_skip6
+01:4ba0 _print_sl_data49
+01:4ba8 _print_sl_out49
+01:4ba8 __check_assert_out6
+01:4bb4 _print_sl_data50
+01:4bb6 _print_sl_out50
+01:4bbe _print_sl_data51
+01:4bc1 _print_sl_out51
+01:4bcb __check_assert_fail7
+01:4bd6 _print_sl_data52
+01:4bd9 _print_sl_out52
+01:4bdc __check_assert_ok7
+01:4be4 _print_sl_data53
+01:4be9 _print_sl_out53
+01:4beb __check_assert_skip7
+01:4bf3 _print_sl_data54
+01:4bfb _print_sl_out54
+01:4bfb __check_assert_out7
+00:0151 _wait_ly_4
+00:0157 _wait_ly_5
+00:01b5 setup_and_wait_mode2
+00:01b5 _wait_ly_6
+00:01d8 fail_halt
+00:01ec _wait_ly_7
+00:01f2 _wait_ly_8
+00:0208 _print_results_halt_1
+00:020b _test_failure_cb_0
+00:0213 _print_sl_data55
+00:021e _print_sl_out55