ARM9: Implement BLX (2)
Jeffrey Pfau jeffrey@endrift.com
Mon, 06 Jun 2016 00:28:27 -0700
5 files changed,
19 insertions(+),
1 deletions(-)
M
src/arm/decoder-arm.c
→
src/arm/decoder-arm.c
@@ -351,6 +351,11 @@ info->op1.reg = opcode & 0x0000000F;
info->operandFormat = ARM_OPERAND_REGISTER_1; info->branchType = ARM_BRANCH_INDIRECT;) +DEFINE_DECODER_ARM(BLX2, BLX, + info->op1.reg = opcode & 0x0000000F; + info->operandFormat = ARM_OPERAND_REGISTER_1; + info->branchType = ARM_BRANCH_LINKED | ARM_BRANCH_INDIRECT;) + // End branch definitions // Begin coprocessor definitions
M
src/arm/decoder.c
→
src/arm/decoder.c
@@ -250,6 +250,7 @@ "b",
"bic", "bkpt", "bl", + "blx", "bx", "cdp", "clz",
M
src/arm/decoder.h
→
src/arm/decoder.h
@@ -158,6 +158,7 @@ ARM_MN_B,
ARM_MN_BIC, ARM_MN_BKPT, ARM_MN_BL, + ARM_MN_BLX, ARM_MN_BX, ARM_MN_CDP, ARM_MN_CLZ,
M
src/arm/emitter-arm.h
→
src/arm/emitter-arm.h
@@ -370,7 +370,7 @@ DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \ DECLARE_INSTRUCTION_ARM(EMITTER, BX), \ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ - DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ + DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), \ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
M
src/arm/isa-arm.c
→
src/arm/isa-arm.c
@@ -613,6 +613,17 @@ if (cpu->executionMode == MODE_THUMB) {
THUMB_WRITE_PC; } else { ARM_WRITE_PC; + + }) +DEFINE_INSTRUCTION_ARM(BLX2, + int rm = opcode & 0x0000000F; + cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM; + _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001); + cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE; + if (cpu->executionMode == MODE_THUMB) { + THUMB_WRITE_PC; + } else { + ARM_WRITE_PC; }) // End branch definitions