all repos — mgba @ afff253928e9364cc0632fc5dfa8ec56f49f9dba

mGBA Game Boy Advance Emulator

GBA Memory: Fix cycle counting for 32-bit load/stores
Jeffrey Pfau jeffrey@endrift.com
Fri, 27 Mar 2015 21:20:13 -0700
commit

afff253928e9364cc0632fc5dfa8ec56f49f9dba

parent

325b1dc35beb85131b44f3fc900f94c9ba08681f

2 files changed, 4 insertions(+), 3 deletions(-)

jump to
M CHANGESCHANGES

@@ -58,6 +58,7 @@ - GBA BIOS: Fix BIOS decompression routines with invalid source addresses

- GBA: Initialize gba.sync to null - GBA: Fix timer initialization - GBA Memory: Fix I cycles that had been moved to ARM7 core + - GBA Memory: Fix cycle counting for 32-bit load/stores Misc: - GBA Audio: Change internal audio sample buffer from 32-bit to 16-bit samples - GBA Memory: Simplify memory API and use fixed bus width
M src/gba/memory.csrc/gba/memory.c

@@ -1180,9 +1180,9 @@ memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];

memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2]; memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4]; - memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0]; - memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1]; - memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2]; + memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0]; + memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1]; + memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2]; memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1; memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;