Start cycle counting
Jeffrey Pfau jeffrey@endrift.com
Sat, 02 Nov 2013 02:52:53 -0700
3 files changed,
63 insertions(+),
27 deletions(-)
M
src/arm/decoder-inlines.h
→
src/arm/decoder-inlines.h
@@ -17,6 +17,15 @@ total += AMOUNT; \
buffer += AMOUNT; \ blen -= AMOUNT; +#define LOAD_CYCLES \ + info->iCycles = 1; \ + info->nDataCycles = 1; + +#define STORE_CYCLES \ + info->sInstructionCycles = 0; \ + info->nInstructionCycles = 1; \ + info->nDataCycles = 1; + static int _decodeRegister(int reg, char* buffer, int blen); static int _decodeRegisterList(int list, char* buffer, int blen); static int _decodePCRelative(uint32_t address, uint32_t pc, char* buffer, int blen);
M
src/arm/decoder-thumb.c
→
src/arm/decoder-thumb.c
@@ -26,7 +26,7 @@ ARM_OPERAND_AFFECTED_1 | \
ARM_OPERAND_REGISTER_2 | \ ARM_OPERAND_IMMEDIATE_3;) -#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC) \ +#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, CYCLES) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \ info->op1.reg = opcode & 0x0007; \ info->memory.baseReg = (opcode >> 3) & 0x0007; \@@ -35,7 +35,14 @@ info->operandFormat = ARM_OPERAND_REGISTER_1 | \
ARM_OPERAND_AFFECTED_1 | \ ARM_OPERAND_MEMORY_2; \ info->memory.format = ARM_MEMORY_REGISTER_BASE | \ - ARM_MEMORY_IMMEDIATE_OFFSET;) + ARM_MEMORY_IMMEDIATE_OFFSET; \ + CYCLES) + +#define DEFINE_IMMEDIATE_5_DECODER_MEM_LOAD_THUMB(NAME, IMMEDIATE, MNEMONIC) \ + DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, LOAD_CYCLES) + +#define DEFINE_IMMEDIATE_5_DECODER_MEM_STORE_THUMB(NAME, IMMEDIATE, MNEMONIC) \ + DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, STORE_CYCLES) #define DEFINE_IMMEDIATE_5_DECODER_THUMB(NAME, MNEMONIC, TYPE) \ COUNT_5(DEFINE_IMMEDIATE_5_DECODER_ ## TYPE ## _THUMB, NAME ## _, MNEMONIC)@@ -43,12 +50,12 @@
DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA) DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA) DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA) -DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM) -DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM) -DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM) -DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM) -DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM) -DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM) +DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM_LOAD) +DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM_LOAD) +DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM_LOAD) +DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM_STORE) +DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM_STORE) +DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM_STORE) #define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \@@ -64,7 +71,7 @@
#define DEFINE_DATA_FORM_1_DECODER_THUMB(NAME) \ COUNT_3(DEFINE_DATA_FORM_1_DECODER_EX_THUMB, NAME ## 3_R, NAME) -DEFINE_DATA_FORM_1_DECODER_THUMB(ADD) +DEFINE_DATA_FORM_1_DECODER_THUMB(ADD) DEFINE_DATA_FORM_1_DECODER_THUMB(SUB) #define DEFINE_DATA_FORM_2_DECODER_EX_THUMB(NAME, IMMEDIATE, MNEMONIC) \@@ -125,7 +132,7 @@ DEFINE_DATA_FORM_5_DECODER_THUMB(CMN, CMN, ARM_OPERAND_NONE)
DEFINE_DATA_FORM_5_DECODER_THUMB(ORR, ORR, ARM_OPERAND_AFFECTED_1) DEFINE_DATA_FORM_5_DECODER_THUMB(MUL, MUL, ARM_OPERAND_AFFECTED_1) DEFINE_DATA_FORM_5_DECODER_THUMB(BIC, BIC, ARM_OPERAND_AFFECTED_1) -DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1) +DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1) #define DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME, H1, H2, MNEMONIC, AFFECTED, CPSR) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \@@ -159,7 +166,7 @@ ARM_OPERAND_AFFECTED_1 | \
ARM_OPERAND_REGISTER_2 | \ ARM_OPERAND_IMMEDIATE_3;) -#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG) \ +#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, CYCLES) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \ info->op1.reg = RD; \ info->memory.baseReg = REG; \@@ -169,19 +176,26 @@ info->operandFormat = ARM_OPERAND_REGISTER_1 | \
ARM_OPERAND_AFFECTED_1 | \ ARM_OPERAND_MEMORY_2; \ info->memory.format = ARM_MEMORY_REGISTER_BASE | \ - ARM_MEMORY_IMMEDIATE_OFFSET;) + ARM_MEMORY_IMMEDIATE_OFFSET; \ + CYCLES;) + +#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_LOAD_THUMB(NAME, RD, MNEMONIC, REG) \ + DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, LOAD_CYCLES) + +#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_STORE_THUMB(NAME, RD, MNEMONIC, REG) \ + DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, STORE_CYCLES) #define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, MNEMONIC, TYPE, REG) \ COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_ ## TYPE ## _THUMB, NAME ## _R, MNEMONIC, REG) -DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM, ARM_PC) -DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM, ARM_SP) -DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM, ARM_SP) +DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM_LOAD, ARM_PC) +DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM_LOAD, ARM_SP) +DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM_STORE, ARM_SP) DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC) DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP) -#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC) \ +#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \ info->memory.offset.reg = RM; \ info->op1.reg = opcode & 0x0007; \@@ -190,19 +204,20 @@ info->operandFormat = ARM_OPERAND_REGISTER_1 | \
ARM_OPERAND_AFFECTED_1 | \ ARM_OPERAND_MEMORY_2; \ info->memory.format = ARM_MEMORY_REGISTER_BASE | \ - ARM_MEMORY_REGISTER_OFFSET;) + ARM_MEMORY_REGISTER_OFFSET; \ + CYCLES;) -#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC) \ - COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC) +#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES) \ + COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB) -DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB, LOAD_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH, LOAD_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB, LOAD_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH, LOAD_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR, STORE_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB, STORE_CYCLES) +DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH, STORE_CYCLES) #define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, SPECIAL_REG, ADDITIONAL_REG) \ DEFINE_THUMB_DECODER(NAME, MNEMONIC, \@@ -303,6 +318,12 @@ info->traps = 0;
info->accessesSpecialRegisters = 0; info->affectsCPSR = 0; info->condition = ARM_CONDITION_AL; + info->sDataCycles = 0; + info->nDataCycles = 0; + info->sInstructionCycles = 1; + info->nInstructionCycles = 0; + info->iCycles = 0; + info->cCycles = 0; ThumbDecoder decoder = _thumbDecoderTable[opcode >> 6]; decoder(opcode, info); }
M
src/arm/decoder.h
→
src/arm/decoder.h
@@ -139,6 +139,12 @@ int traps;
int accessesSpecialRegisters; int affectsCPSR; int condition; + int sDataCycles; + int nDataCycles; + int sInstructionCycles; + int nInstructionCycles; + int iCycles; + int cCycles; }; void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);