Filler for more instructions
Jeffrey Pfau jeffrey@endrift.com
Sat, 06 Apr 2013 00:32:01 -0700
1 files changed,
185 insertions(+),
42 deletions(-)
jump to
M
src/arm.c
→
src/arm.c
@@ -31,7 +31,7 @@ cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
} } -static const ARMInstruction armTable[0xF000]; +static const ARMInstruction armTable[0x10000]; static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) { if (executionMode == cpu->executionMode) {@@ -193,6 +193,28 @@ DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \ DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY) +#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, BODY) \ + DEFINE_INSTRUCTION_ARM(NAME ## ADDRESS, \ + BODY;) + +#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, , BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, W, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, U, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, UW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, P, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PU, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PUW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, I, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IU, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IUW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IP, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPW, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPU, BODY) \ + DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPUW, BODY) + // Begin ALU definitions DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \@@ -267,14 +289,14 @@ // End multiply definitions
// Begin load/store definitions -DEFINE_INSTRUCTION_ARM(LDR,) -DEFINE_INSTRUCTION_ARM(LDRB,) -DEFINE_INSTRUCTION_ARM(LDRH,) -DEFINE_INSTRUCTION_ARM(LDRSB,) -DEFINE_INSTRUCTION_ARM(LDRSH,) -DEFINE_INSTRUCTION_ARM(STR,) -DEFINE_INSTRUCTION_ARM(STRB,) -DEFINE_INSTRUCTION_ARM(STRH,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRH,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSB,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSH,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB,) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRH,) DEFINE_INSTRUCTION_ARM(SWP,) DEFINE_INSTRUCTION_ARM(SWPB,)@@ -318,39 +340,43 @@ DECLARE_INSTRUCTION_ARM(COND, EX3), \
DECLARE_INSTRUCTION_ARM(COND, ALU), \ DECLARE_INSTRUCTION_ARM(COND, EX4) +#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \ + DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) \ + DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) + #define DECLARE_COND_BLOCK(COND) \ DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \ DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRH, LDRSB, LDRSH), \ - DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRH, ILL, ILL), \ - DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH), \ + DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRHW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRHW, LDRSBW, LDRSHW), \ + DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \ + DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRHIW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRHIW, LDRSBIW, LDRSHIW), \ + DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \ + DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRHUW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRHUW, LDRSBUW, LDRSHUW), \ + DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \ + DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRHIUW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \ + DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \ + DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHPW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \ + DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \ + DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHIPW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \ + DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRHPU, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \ + DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRHPUW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \ + DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRHIPU, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \ + DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRHIPUW, ILL, ILL), \ + DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \@@ -382,9 +408,125 @@ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \ - DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS) + DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)//, \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, ), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, W), \ + // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, W), \ + // DECLARE_ARM_BRANCH_BLOCK(COND, B), \ + // DECLARE_ARM_BRANCH_BLOCK(COND, BL), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \ + // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \ + // DECLARE_ARM_COPROCESSOR_BLOCK(CDP, MCR), \ + // DECLARE_ARM_SWI_BLOCK -static const ARMInstruction armTable[0xF000] = { +static const ARMInstruction armTable[0x10000] = { DECLARE_COND_BLOCK(EQ), DECLARE_COND_BLOCK(NE), DECLARE_COND_BLOCK(CS),@@ -399,5 +541,6 @@ DECLARE_COND_BLOCK(GE),
DECLARE_COND_BLOCK(LT), DECLARE_COND_BLOCK(GT), DECLARE_COND_BLOCK(LE), - DECLARE_COND_BLOCK(AL) + DECLARE_COND_BLOCK(AL)//, + //DECLARE_EMPTY_BLOCK };