git rekt — mgba.git: 5018364c0140a0eb8ae8d3368651edd66784a4d9

@@ -1,206 +1,144 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0150 _wait_ly_4
-00:0156 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0150 main@wait_ly_5
+00:0156 main@wait_ly_6
 00:0180 test_finish
-00:01c4 wram_test
-00:01d3 hiram_test
-00:01d3 test_round1
-00:01d5 _wait_ly_6
-00:01db _wait_ly_7
-00:01f0 finish_round1
-00:01ff test_round2
-00:0201 _wait_ly_8
-00:0207 _wait_ly_9
-00:021d finish_round2
-00:c014 result_tmp
-00:c016 result_round1
+00:01c9 wram_test
+00:01d8 hiram_test
+00:01d8 test_round1
+00:01da test_round1@wait_ly_7
+00:01e0 test_round1@wait_ly_8
+00:01f5 finish_round1
+00:0204 test_round2
+00:0206 test_round2@wait_ly_9
+00:020c test_round2@wait_ly_10
+00:0222 finish_round2
+00:ff91 result_tmp
+00:ff93 result_round1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_result_tmp
+00000002 _sizeof_result_round1
+00000030 _sizeof_main
+00000049 _sizeof_test_finish
+0000000f _sizeof_wram_test
+00000000 _sizeof_hiram_test
+0000001d _sizeof_test_round1
+0000000f _sizeof_finish_round1
+0000001e _sizeof_test_round2

M cinema/gb/mooneye-gb/acceptance/bits/mem_oam/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/bits/mem_oam/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.gb → cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.gb

M cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym → cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym

@@ -1,212 +1,50 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:016f test_finish
-00:0183 _wait_ly_4
-00:0189 _wait_ly_5
-00:019f _print_results_halt_1
-00:01a2 _test_ok_cb_0
-00:01aa _print_sl_data55
-00:01b2 _print_sl_out55
-00:01b5 fail_1
-00:01c9 _wait_ly_6
-00:01cf _wait_ly_7
-00:01e5 _print_results_halt_2
-00:01e8 _test_failure_cb_0
-00:01f0 _print_sl_data56
-00:01fd _print_sl_out56
-00:0200 fail_0
-00:0214 _wait_ly_8
-00:021a _wait_ly_9
-00:0230 _print_results_halt_3
-00:0233 _test_failure_cb_1
-00:023b _print_sl_data57
-00:0248 _print_sl_out57
+00:0176 test_finish@quit_inline_1
+00:0187 fail_1
+00:018e fail_1@quit_inline_2
+00:01a4 fail_0
+00:01ab fail_0@quit_inline_3
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000001f _sizeof_main
+00000018 _sizeof_test_finish
+0000001d _sizeof_fail_1

M cinema/gb/mooneye-gb/acceptance/bits/reg_f/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/bits/reg_f/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/bits/reg_f/test.gb → cinema/gb/mooneye-gb/acceptance/bits/reg_f/test.gb

M cinema/gb/mooneye-gb/acceptance/bits/reg_f/test.sym → cinema/gb/mooneye-gb/acceptance/bits/reg_f/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/reg_f.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/reg_f.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0160 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000010 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/test.gb → cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/test.gb

M cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/test.sym → cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/test.sym

@@ -1,194 +1,32 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/unused_hwio-GS.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/unused_hwio-GS.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c017 regs_save
-00:c017 regs_save.f
-00:c018 regs_save.a
-00:c019 regs_save.c
-00:c01a regs_save.b
-00:c01b regs_save.e
-00:c01c regs_save.d
-00:c01d regs_save.l
-00:c01e regs_save.h
-00:c01f regs_flags
-00:c020 regs_assert
-00:c020 regs_assert.f
-00:c021 regs_assert.a
-00:c022 regs_assert.c
-00:c023 regs_assert.b
-00:c024 regs_assert.e
-00:c025 regs_assert.d
-00:c026 regs_assert.l
-00:c027 regs_assert.h
-00:c028 memdump_len
-00:c029 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
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-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0161 _test_data_0
 00:0177 _finish_0
 00:0187 _test_data_1
@@ -497,39 +335,357 @@ 00:17f1 _test_data_152
 00:1807 _finish_152
 00:1817 _test_data_153
 00:182d _finish_153
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-00:1847 _wait_ly_5
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-00:1870 _print_sl_out55
-00:1873 run_testcase
-00:189e _wait_ly_6
-00:18a4 _wait_ly_7
-00:18ba _print_results_halt_2
-00:18bd test_failure_cb
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-00:18df _print_sl_data57
-00:18e3 _print_sl_out57
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-00:1901 _print_sl_out58
-00:190f _print_sl_data59
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-00:192d _print_sl_data60
-00:193a _print_sl_out60
-00:194b _print_sl_data61
-00:1958 _print_sl_out61
-00:195e fetch_test_data
-00:1978 print_got
-00:198a _print_zero
-00:198e _print_one
-00:1990 _print_bit
-00:1999 _skip
-00:199a _next
-00:c000 test_addr
-00:c002 test_got
-00:c003 test_reg
-00:c004 test_mask
-00:c005 test_str_write
-00:c00e test_str_expect
+00:1834 _finish_153@quit_inline_1
+00:1845 run_testcase
+00:1863 run_testcase@quit_inline_2
+00:18e6 fetch_test_data
+00:1900 print_got
+00:1912 _print_zero
+00:1916 _print_one
+00:1918 _print_bit
+00:1921 _skip
+00:1922 _next
+00:ff80 test_addr
+00:ff82 test_got
+00:ff83 test_reg
+00:ff84 test_mask
+00:ff85 test_str_write
+00:ff8e test_str_expect
+
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A cinema/gb/mooneye-gb/acceptance/boot_div-S/manifest.yml

@@ -0,0 +1,3 @@
+config:
+  gb.model: SGB
+fail: true

A cinema/gb/mooneye-gb/acceptance/boot_div-S/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-S.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
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+01:487a check_asserts_cb@skip0
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+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
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+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
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+01:4ae6 quit@success
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+01:4b22 quit@halt
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+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
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+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
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+0000000f _sizeof_disable_lcd_safe
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A cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/test.gb

A cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmg0.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
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+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
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+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
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+01:4ad6 quit@wait_ly_3
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+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
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+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
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+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

A cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmgABCmgb.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

A cinema/gb/mooneye-gb/acceptance/boot_div2-S/manifest.yml

@@ -0,0 +1,3 @@
+config:
+  gb.model: SGB
+fail: true

A cinema/gb/mooneye-gb/acceptance/boot_div2-S/test.gb

A cinema/gb/mooneye-gb/acceptance/boot_div2-S/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div2-S.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

M cinema/gb/mooneye-gb/acceptance/boot_hwio-S/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/boot_hwio-S/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml → cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: SGB}
+config:
+  gb.model: SGB

M cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.gb → cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.sym → cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.sym

@@ -1,212 +1,57 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

M cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/test.gb → cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/test.sym → cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/test.sym

@@ -1,212 +1,57 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmg0.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmg0.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

D cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma/reg_read/test.gb

D cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.sav

D cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.sym

@@ -1,212 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCXmgb.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem

A cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym

@@ -0,0 +1,57 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCmgb.gb".
+
+[labels]
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

D cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/test.gb

D cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/test.sym

@@ -1,198 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg.gb".
-
-[labels]
-0001:4bf2 print_load_font
-0001:4bff print_string
-0001:4c09 print_a
-0001:4c13 print_newline
-0001:4c1e print_digit
-0001:4c2b print_regs
-0001:4c34 _print_sl_data0
-0001:4c3a _print_sl_out0
-0001:4c47 _print_sl_data1
-0001:4c4d _print_sl_out1
-0001:4c5f _print_sl_data2
-0001:4c65 _print_sl_out2
-0001:4c72 _print_sl_data3
-0001:4c78 _print_sl_out3
-0001:4c8a _print_sl_data4
-0001:4c90 _print_sl_out4
-0001:4c9d _print_sl_data5
-0001:4ca3 _print_sl_out5
-0001:4cb5 _print_sl_data6
-0001:4cbb _print_sl_out6
-0001:4cc8 _print_sl_data7
-0001:4cce _print_sl_out7
-0001:4000 font
-0000:c000 regs_save
-0000:c000 regs_save.f
-0000:c001 regs_save.a
-0000:c002 regs_save.c
-0000:c003 regs_save.b
-0000:c004 regs_save.e
-0000:c005 regs_save.d
-0000:c006 regs_save.l
-0000:c007 regs_save.h
-0000:c008 regs_flags
-0000:c009 regs_assert
-0000:c009 regs_assert.f
-0000:c00a regs_assert.a
-0000:c00b regs_assert.c
-0000:c00c regs_assert.b
-0000:c00d regs_assert.e
-0000:c00e regs_assert.d
-0000:c00f regs_assert.l
-0000:c010 regs_assert.h
-0000:c011 memdump_len
-0000:c012 memdump_addr
-0001:47f0 memcpy
-0001:47f9 memset
-0001:4802 clear_vram
-0001:480d reset_screen
-0001:481a process_results
-0001:481f _wait_ly_0
-0001:4825 _wait_ly_1
-0001:4841 _wait_ly_2
-0001:4847 _wait_ly_3
-0001:4860 _process_results_cb
-0001:486b _print_sl_data8
-0001:4875 _print_sl_out8
-0001:488f _print_sl_data9
-0001:489a _print_sl_out9
-0001:48b2 _print_sl_data10
-0001:48be _print_sl_out10
-0001:48bf dump_mem
-0001:48cf _wait_ly_4
-0001:48d5 _wait_ly_5
-0001:48f1 _dump_mem_line
-0001:491b _check_asserts
-0001:4929 _print_sl_data11
-0001:492c _print_sl_out11
-0001:4938 _print_sl_data12
-0001:493a _print_sl_out12
-0001:4942 _print_sl_data13
-0001:4945 _print_sl_out13
-0001:494f __check_assert_fail0
-0001:495a _print_sl_data14
-0001:495d _print_sl_out14
-0001:4960 __check_assert_ok0
-0001:4968 _print_sl_data15
-0001:496d _print_sl_out15
-0001:496f __check_assert_skip0
-0001:4977 _print_sl_data16
-0001:497f _print_sl_out16
-0001:497f __check_assert_out0
-0001:498b _print_sl_data17
-0001:498d _print_sl_out17
-0001:4995 _print_sl_data18
-0001:4998 _print_sl_out18
-0001:49a2 __check_assert_fail1
-0001:49ad _print_sl_data19
-0001:49b0 _print_sl_out19
-0001:49b3 __check_assert_ok1
-0001:49bb _print_sl_data20
-0001:49c0 _print_sl_out20
-0001:49c2 __check_assert_skip1
-0001:49ca _print_sl_data21
-0001:49d2 _print_sl_out21
-0001:49d2 __check_assert_out1
-0001:49dd _print_sl_data22
-0001:49e0 _print_sl_out22
-0001:49ec _print_sl_data23
-0001:49ee _print_sl_out23
-0001:49f6 _print_sl_data24
-0001:49f9 _print_sl_out24
-0001:4a03 __check_assert_fail2
-0001:4a0e _print_sl_data25
-0001:4a11 _print_sl_out25
-0001:4a14 __check_assert_ok2
-0001:4a1c _print_sl_data26
-0001:4a21 _print_sl_out26
-0001:4a23 __check_assert_skip2
-0001:4a2b _print_sl_data27
-0001:4a33 _print_sl_out27
-0001:4a33 __check_assert_out2
-0001:4a3f _print_sl_data28
-0001:4a41 _print_sl_out28
-0001:4a49 _print_sl_data29
-0001:4a4c _print_sl_out29
-0001:4a56 __check_assert_fail3
-0001:4a61 _print_sl_data30
-0001:4a64 _print_sl_out30
-0001:4a67 __check_assert_ok3
-0001:4a6f _print_sl_data31
-0001:4a74 _print_sl_out31
-0001:4a76 __check_assert_skip3
-0001:4a7e _print_sl_data32
-0001:4a86 _print_sl_out32
-0001:4a86 __check_assert_out3
-0001:4a91 _print_sl_data33
-0001:4a94 _print_sl_out33
-0001:4aa0 _print_sl_data34
-0001:4aa2 _print_sl_out34
-0001:4aaa _print_sl_data35
-0001:4aad _print_sl_out35
-0001:4ab7 __check_assert_fail4
-0001:4ac2 _print_sl_data36
-0001:4ac5 _print_sl_out36
-0001:4ac8 __check_assert_ok4
-0001:4ad0 _print_sl_data37
-0001:4ad5 _print_sl_out37
-0001:4ad7 __check_assert_skip4
-0001:4adf _print_sl_data38
-0001:4ae7 _print_sl_out38
-0001:4ae7 __check_assert_out4
-0001:4af3 _print_sl_data39
-0001:4af5 _print_sl_out39
-0001:4afd _print_sl_data40
-0001:4b00 _print_sl_out40
-0001:4b0a __check_assert_fail5
-0001:4b15 _print_sl_data41
-0001:4b18 _print_sl_out41
-0001:4b1b __check_assert_ok5
-0001:4b23 _print_sl_data42
-0001:4b28 _print_sl_out42
-0001:4b2a __check_assert_skip5
-0001:4b32 _print_sl_data43
-0001:4b3a _print_sl_out43
-0001:4b3a __check_assert_out5
-0001:4b45 _print_sl_data44
-0001:4b48 _print_sl_out44
-0001:4b54 _print_sl_data45
-0001:4b56 _print_sl_out45
-0001:4b5e _print_sl_data46
-0001:4b61 _print_sl_out46
-0001:4b6b __check_assert_fail6
-0001:4b76 _print_sl_data47
-0001:4b79 _print_sl_out47
-0001:4b7c __check_assert_ok6
-0001:4b84 _print_sl_data48
-0001:4b89 _print_sl_out48
-0001:4b8b __check_assert_skip6
-0001:4b93 _print_sl_data49
-0001:4b9b _print_sl_out49
-0001:4b9b __check_assert_out6
-0001:4ba7 _print_sl_data50
-0001:4ba9 _print_sl_out50
-0001:4bb1 _print_sl_data51
-0001:4bb4 _print_sl_out51
-0001:4bbe __check_assert_fail7
-0001:4bc9 _print_sl_data52
-0001:4bcc _print_sl_out52
-0001:4bcf __check_assert_ok7
-0001:4bd7 _print_sl_data53
-0001:4bdc _print_sl_out53
-0001:4bde __check_assert_skip7
-0001:4be6 _print_sl_data54
-0001:4bee _print_sl_out54
-0001:4bee __check_assert_out7
-0000:01d2 invalid_sp
-0000:01d7 _wait_ly_6
-0000:01dd _wait_ly_7
-0000:01f9 _wait_ly_8
-0000:01ff _wait_ly_9
-0000:0218 _test_failure_cb_0
-0000:0220 _print_sl_data55
-0000:0231 _print_sl_out55
-0000:c014 sp_save

M cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.gb → cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym → cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

A cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.gb

A cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym

@@ -0,0 +1,125 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABC.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

D cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma/basic/test.gb

D cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/test.sym

@@ -1,199 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABCX.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save

M cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/manifest.yml → cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: MGB}
+config:
+  gb.model: MGB

M cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.gb → cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym → cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/manifest.yml → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: SGB}
+config:
+  gb.model: SGB

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/test.gb → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/test.sym → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/manifest.yml → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: SGB2}
+config:
+  gb.model: SGB2

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/test.gb → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/test.gb

M cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/test.sym → cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/call_cc_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/call_cc_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/call_cc_timing/test.gb → cinema/gb/mooneye-gb/acceptance/call_cc_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/call_cc_timing/test.sym → cinema/gb/mooneye-gb/acceptance/call_cc_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

M cinema/gb/mooneye-gb/acceptance/call_cc_timing2/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/call_cc_timing2/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.gb → cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.gb

M cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym → cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym

@@ -1,204 +1,138 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01cf hiram_test
-00:01d2 _wait_ly_6
-00:01d8 _wait_ly_7
-00:01ec finish_round1
-00:01ed _wait_ly_8
-00:01f3 _wait_ly_9
-00:0208 finish_round2
-00:0209 _wait_ly_10
-00:020f _wait_ly_11
-00:0225 finish_round3
+00:01d2 hiram_test
+00:01d5 hiram_test@wait_ly_7
+00:01db hiram_test@wait_ly_8
+00:01ef finish_round1
+00:01f0 finish_round1@wait_ly_9
+00:01f6 finish_round1@wait_ly_10
+00:020b finish_round2
+00:020c finish_round2@wait_ly_11
+00:0212 finish_round2@wait_ly_12
+00:0228 finish_round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+0000005b _sizeof_test_finish
+0000001d _sizeof_hiram_test
+0000001c _sizeof_finish_round1
+0000001d _sizeof_finish_round2

M cinema/gb/mooneye-gb/acceptance/call_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/call_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/call_timing/test.gb → cinema/gb/mooneye-gb/acceptance/call_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/call_timing/test.sym → cinema/gb/mooneye-gb/acceptance/call_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

M cinema/gb/mooneye-gb/acceptance/call_timing2/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/call_timing2/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/call_timing2/test.gb → cinema/gb/mooneye-gb/acceptance/call_timing2/test.gb

M cinema/gb/mooneye-gb/acceptance/call_timing2/test.sym → cinema/gb/mooneye-gb/acceptance/call_timing2/test.sym

@@ -1,204 +1,138 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01cf hiram_test
-00:01d2 _wait_ly_6
-00:01d8 _wait_ly_7
-00:01ec finish_round1
-00:01ed _wait_ly_8
-00:01f3 _wait_ly_9
-00:0208 finish_round2
-00:0209 _wait_ly_10
-00:020f _wait_ly_11
-00:0225 finish_round3
+00:01d2 hiram_test
+00:01d5 hiram_test@wait_ly_7
+00:01db hiram_test@wait_ly_8
+00:01ef finish_round1
+00:01f0 finish_round1@wait_ly_9
+00:01f6 finish_round1@wait_ly_10
+00:020b finish_round2
+00:020c finish_round2@wait_ly_11
+00:0212 finish_round2@wait_ly_12
+00:0228 finish_round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
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+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+0000005b _sizeof_test_finish
+0000001d _sizeof_hiram_test
+0000001c _sizeof_finish_round1
+0000001d _sizeof_finish_round2

M cinema/gb/mooneye-gb/acceptance/di_timing-GS/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/di_timing-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/di_timing-GS/test.gb → cinema/gb/mooneye-gb/acceptance/di_timing-GS/test.gb

M cinema/gb/mooneye-gb/acceptance/di_timing-GS/test.sym → cinema/gb/mooneye-gb/acceptance/di_timing-GS/test.sym

@@ -1,228 +1,67 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/di_timing-GS.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/di_timing-GS.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0158 _wait_ly_4
-00:015e _wait_ly_5
+00:0150 main
+00:0158 main@wait_ly_5
+00:015e main@wait_ly_6
 00:016d test_round1
 00:0177 _delay_long_time_0
 00:0186 finish_round1
-00:0189 _wait_ly_6
-00:018f _wait_ly_7
+00:0189 finish_round1@wait_ly_7
+00:018f finish_round1@wait_ly_8
 00:019e test_round2
 00:01a8 _delay_long_time_1
 00:01b4 test_finish
-00:01c8 _wait_ly_8
-00:01ce _wait_ly_9
-00:01e4 _print_results_halt_1
-00:01e7 _test_ok_cb_0
-00:01ef _print_sl_data55
-00:01f7 _print_sl_out55
-00:01fa fail_halt
-00:020e _wait_ly_10
-00:0214 _wait_ly_11
-00:022a _print_results_halt_2
-00:022d _test_failure_cb_0
-00:0235 _print_sl_data56
-00:0240 _print_sl_out56
-00:0243 fail_round1
-00:0257 _wait_ly_12
-00:025d _wait_ly_13
-00:0273 _print_results_halt_3
-00:0276 _test_failure_cb_1
-00:027e _print_sl_data57
-00:028c _print_sl_out57
-00:028f fail_round2
-00:02a3 _wait_ly_14
-00:02a9 _wait_ly_15
-00:02bf _print_results_halt_4
-00:02c2 _test_failure_cb_2
-00:02ca _print_sl_data58
-00:02d8 _print_sl_out58
+00:01bb test_finish@quit_inline_1
+00:01cc fail_halt
+00:01d3 fail_halt@quit_inline_2
+00:01e7 fail_round1
+00:01ee fail_round1@quit_inline_3
+00:0205 fail_round2
+00:020c fail_round2@quit_inline_4
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000001d _sizeof_main
+0000000a _sizeof_test_round1
+0000000f _sizeof__delay_long_time_0
+00000018 _sizeof_finish_round1
+0000000a _sizeof_test_round2
+0000000c _sizeof__delay_long_time_1
+00000018 _sizeof_test_finish
+0000001b _sizeof_fail_halt
+0000001e _sizeof_fail_round1

M cinema/gb/mooneye-gb/acceptance/div_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/div_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/div_timing/test.gb → cinema/gb/mooneye-gb/acceptance/div_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/div_timing/test.sym → cinema/gb/mooneye-gb/acceptance/div_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/div_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/div_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0232 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+000000e2 _sizeof_main

A cinema/gb/mooneye-gb/acceptance/ei_sequence/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ei_sequence/test.gb

A cinema/gb/mooneye-gb/acceptance/ei_sequence/test.sym

@@ -0,0 +1,127 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_sequence.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01a0 test
+00:01b2 fail
+00:01b9 fail@quit_inline_1
+00:01d0 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000050 _sizeof_main
+00000012 _sizeof_test
+0000001e _sizeof_fail

M cinema/gb/mooneye-gb/acceptance/ei_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/ei_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/ei_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ei_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/ei_timing/test.sym → cinema/gb/mooneye-gb/acceptance/ei_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
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-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
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-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
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-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
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-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
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-01:4928 _check_asserts
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-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
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-01:498c __check_assert_out0
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-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
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-01:49af __check_assert_fail1
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-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
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-01:4a03 _print_sl_data24
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-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
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-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
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-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
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-01:4ad5 __check_assert_ok4
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-01:4af4 __check_assert_out4
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-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
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-01:4b61 _print_sl_data45
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-01:4b78 __check_assert_fail6
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-01:4b89 __check_assert_ok6
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-01:4b96 _print_sl_out48
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-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0160 test_finish
+
+[definitions]
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+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
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+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000010 _sizeof_main

D cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/manifest.yml → cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/manifest.yml

M cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma/sources-dmgABCmgbS/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/test.sym

@@ -1,219 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/hblank_ly_scx_timing-GS.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
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-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
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-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
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-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
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-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
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-01:496d __check_assert_ok0
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-01:498c __check_assert_out0
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-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
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-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
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-01:4a56 _print_sl_data29
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-01:4a93 __check_assert_out3
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-01:4af4 __check_assert_out4
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-01:4bfb __check_assert_out7
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-00:0157 _wait_ly_5
-00:03a2 _wait_ly_6
-00:03a8 _wait_ly_7
-00:03be _print_results_halt_1
-00:03c1 _test_ok_cb_0
-00:03c9 _print_sl_data55
-00:03d1 _print_sl_out55
-00:03d4 test_fail
-00:0404 _wait_ly_8
-00:040a _wait_ly_9
-00:0420 _print_results_halt_2
-00:0423 _test_failure_dump_cb_0
-00:042e _print_sl_data56
-00:0438 _print_sl_out56
-00:044c _print_sl_data57
-00:0458 _print_sl_out57
-00:045b standard_delay
-00:0473 setup_and_wait
-00:0473 _wait_ly_10
-00:0479 _wait_ly_11
-00:048d fail_halt
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-00:04a7 _wait_ly_13
-00:04bd _print_results_halt_3
-00:04c0 _test_failure_cb_0
-00:04c8 _print_sl_data58
-00:04d3 _print_sl_out58

D cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/test.gb → cinema/gb/mooneye-gb/misc/boot_div-A/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/test.sym

@@ -1,203 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_1_2_timing-GS.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
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-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
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-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
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-01:49bd _print_sl_out19
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-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
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-01:4a21 __check_assert_ok2
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-01:4a40 __check_assert_out2
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-01:4a63 __check_assert_fail3
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-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
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-00:01fe _test_failure_cb_0
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-00:0211 _print_sl_out55

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/lcdon_timing-dmgABCmgbS/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/test.sym

@@ -1,203 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_0_timing.gb".
-
-[labels]
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-01:4c20 print_newline
-01:4c2b print_digit
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-01:4c41 _print_sl_data0
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-01:4c5a _print_sl_out1
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-01:4000 font
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-00:c010 regs_assert.h
-00:c011 memdump_len
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-01:48df dump_mem
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-01:4bc1 _print_sl_out51
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-00:020c _test_failure_cb_0
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-00:021f _print_sl_out55

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/intr_2_0_timing/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
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-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
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-00:c011 memdump_len
-00:c012 memdump_addr
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-01:48df dump_mem
-01:48fe _dump_mem_line
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-01:495c __check_assert_fail0
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-01:496d __check_assert_ok0
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-01:498c __check_assert_out0
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-01:49cd _print_sl_out20
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-00:0270 _print_sl_out55

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing_sprites/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing_sprites/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing_sprites/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing_sprites/test.sym

@@ -1,437 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing_sprites.gb".
-
-[labels]
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-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
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-01:4000 font
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D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode3_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode3_timing/test.gb → cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode3_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode3_timing.gb".
-
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-00:021e _print_sl_out55

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_oam_ok_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/intr_2_oam_ok_timing/test.gb → cinema/gb/mooneye-gb/acceptance/boot_div-S/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/intr_2_oam_ok_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_oam_ok_timing.gb".
-
-[labels]
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-01:4c41 _print_sl_data0
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-00:0247 _wait_ly_8
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-00:0273 _print_sl_out55

M cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/manifest.yml → cinema/gb/mooneye-gb/acceptance/ppu/lcdon_timing-dmgABCmgbS/manifest.yml

M cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/test.sym

@@ -1,236 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/lcdon_timing-dmgABCXmgbS.gb".
-
-[labels]
-01:5087 print_load_font
-01:5094 print_string
-01:509e print_a
-01:50a8 print_newline
-01:50b3 print_digit
-01:50c0 print_regs
-01:50c9 _print_sl_data0
-01:50cf _print_sl_out0
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-01:50f4 _print_sl_data2
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-01:511f _print_sl_data4
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-01:4000 font
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-00:c022 regs_save.d
-00:c023 regs_save.l
-00:c024 regs_save.h
-00:c025 regs_flags
-00:c026 regs_assert
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-00:c028 regs_assert.c
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-00:c02e memdump_len
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-01:4810 clear_vram
-01:481a clear_oam
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-01:4839 reset_screen
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-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
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-01:4880 _process_results_cb
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-01:4895 _print_sl_out8
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-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
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-01:494f _print_sl_data13
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-01:49cd _print_sl_out20
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-01:49df _print_sl_out21
-01:49df __check_assert_out1
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-01:4a10 __check_assert_fail2
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-01:4a21 __check_assert_ok2
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-01:4a40 _print_sl_out27
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-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
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-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:015a test_ly
-00:0166 test_stat_lyc0
-00:0175 test_stat_lyc1
-00:0185 test_oam_access
-00:0191 test_vram_access
-00:019d test_finish
-00:01b1 _wait_ly_4
-00:01b7 _wait_ly_5
-00:01cd _print_results_halt_1
-00:01d0 _test_ok_cb_0
-00:01d8 _print_sl_data55
-00:01e0 _print_sl_out55
-01:4ed8 cycle_counts
-01:4ef0 expect_ly
-01:4f0b expect_stat_lyc0
-01:4f2e expect_stat_lyc1
-01:4f51 expect_oam_access
-01:4f74 expect_vram_access
-01:4f98 verify_results
-01:4faf verify_fail
-01:4fdd _wait_ly_6
-01:4fe3 _wait_ly_7
-01:4ff9 _print_results_halt_2
-01:4ffc _verify_fail_cb
-01:5004 _print_sl_data56
-01:5012 _print_sl_out56
-01:502e _print_sl_data57
-01:503a _print_sl_out57
-01:5055 _print_sl_data58
-01:5061 _print_sl_out58
-01:5072 _print_sl_data59
-01:507e _print_sl_out59
-00:c000 v_pass1_results
-00:c008 v_pass2_results
-00:c010 v_pass3_results
-00:c018 v_fail_round
-00:c019 v_fail_expect
-00:c01a v_fail_actual
-00:c01b v_fail_str
-00:c01b v_fail_str_l
-00:c01c v_fail_str_h
-01:4bff test_passes
-01:4bff test_pass1
-01:4cf1 test_pass2
-01:4de4 test_pass3

M cinema/gb/mooneye-gb/acceptance/gpu/lcdon_write_timing-GS/manifest.yml → cinema/gb/mooneye-gb/acceptance/ppu/lcdon_write_timing-GS/manifest.yml

M cinema/gb/mooneye-gb/acceptance/gpu/lcdon_write_timing-GS/test.gb → cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/lcdon_write_timing-GS/test.sym

@@ -1,230 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/lcdon_write_timing-GS.gb".
-
-[labels]
-01:4d3c print_load_font
-01:4d49 print_string
-01:4d53 print_a
-01:4d5d print_newline
-01:4d68 print_digit
-01:4d75 print_regs
-01:4d7e _print_sl_data0
-01:4d84 _print_sl_out0
-01:4d91 _print_sl_data1
-01:4d97 _print_sl_out1
-01:4da9 _print_sl_data2
-01:4daf _print_sl_out2
-01:4dbc _print_sl_data3
-01:4dc2 _print_sl_out3
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-01:4dda _print_sl_out4
-01:4de7 _print_sl_data5
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-01:4dff _print_sl_data6
-01:4e05 _print_sl_out6
-01:4e12 _print_sl_data7
-01:4e18 _print_sl_out7
-01:4000 font
-00:c144 regs_save
-00:c144 regs_save.f
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-00:c146 regs_save.c
-00:c147 regs_save.b
-00:c148 regs_save.e
-00:c149 regs_save.d
-00:c14a regs_save.l
-00:c14b regs_save.h
-00:c14c regs_flags
-00:c14d regs_assert
-00:c14d regs_assert.f
-00:c14e regs_assert.a
-00:c14f regs_assert.c
-00:c150 regs_assert.b
-00:c151 regs_assert.e
-00:c152 regs_assert.d
-00:c153 regs_assert.l
-00:c154 regs_assert.h
-00:c155 memdump_len
-00:c156 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
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-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:015a test_oam_access
-00:0166 test_vram_access
-00:0172 test_finish
-00:0186 _wait_ly_4
-00:018c _wait_ly_5
-00:01a2 _print_results_halt_1
-00:01a5 _test_ok_cb_0
-00:01ad _print_sl_data55
-00:01b5 _print_sl_out55
-01:4bff nop_counts
-01:4c12 expect_oam_access
-01:4c2f expect_vram_access
-01:4c4d verify_results
-01:4c64 verify_fail
-01:4c92 _wait_ly_6
-01:4c98 _wait_ly_7
-01:4cae _print_results_halt_2
-01:4cb1 _verify_fail_cb
-01:4cb9 _print_sl_data56
-01:4cc7 _print_sl_out56
-01:4ce3 _print_sl_data57
-01:4cef _print_sl_out57
-01:4d0a _print_sl_data58
-01:4d16 _print_sl_out58
-01:4d27 _print_sl_data59
-01:4d33 _print_sl_out59
-00:c000 v_test_code
-00:c12c v_test_results
-00:c13f v_fail_round
-00:c140 v_fail_expect
-00:c141 v_fail_actual
-00:c142 v_fail_str
-00:c142 v_fail_str_l
-00:c143 v_fail_str_h
-01:4e22 run_tests
-01:4e3b test_case
-01:4e6f test_case_prologue
-01:4e73 test_case_epilogue
-01:4e75 test_case_end

D cinema/gb/mooneye-gb/acceptance/gpu/stat_irq_blocking/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/stat_irq_blocking/test.gb → cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/stat_irq_blocking/test.sym

@@ -1,219 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/stat_irq_blocking.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
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-01:4b17 __check_assert_fail5
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-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
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-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 test_round1
-00:0156 _wait_ly_4
-00:015c _wait_ly_5
-00:016b fail_round1
-00:0180 _wait_ly_6
-00:0186 _wait_ly_7
-00:019c _print_results_halt_1
-00:019f _test_failure_cb_0
-00:01a7 _print_sl_data55
-00:01b9 _print_sl_out55
-00:01bc test_round2
-00:01c6 ly_iteration
-00:01dc finish_round2
-00:01f1 _wait_ly_8
-00:01f7 _wait_ly_9
-00:020d _print_results_halt_2
-00:0210 _test_ok_cb_0
-00:0218 _print_sl_data56
-00:0220 _print_sl_out56
-00:0223 fail_round2
-00:0250 _wait_ly_10
-00:0256 _wait_ly_11
-00:026c _print_results_halt_3
-00:026f _test_failure_dump_cb_0
-00:027a _print_sl_data57
-00:0284 _print_sl_out57
-00:0298 _print_sl_data58
-00:02a4 _print_sl_out58

D cinema/gb/mooneye-gb/acceptance/gpu/vblank_stat_intr-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/gpu/vblank_stat_intr-GS/test.gb → cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.gb

D cinema/gb/mooneye-gb/acceptance/gpu/vblank_stat_intr-GS/test.sym

@@ -1,216 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/vblank_stat_intr-GS.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
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-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
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-01:4a93 __check_assert_out3
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-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
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-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0169 fail_halt
-00:017d _wait_ly_4
-00:0183 _wait_ly_5
-00:0199 _print_results_halt_1
-00:019c _test_failure_cb_0
-00:01a4 _print_sl_data55
-00:01a9 _print_sl_out55
-00:01ac test_round1
-00:01b8 _wait_ly_6
-00:0203 finish_round1
-00:0221 test_round2
-00:022d _wait_ly_7
-00:0279 finish_round2
-00:029b test_round3
-00:02a7 _wait_ly_8
-00:02f2 finish_round3
-00:0310 test_round4
-00:031c _wait_ly_9
-00:0368 finish_round4
-00:036a test_finish
-00:c014 intr_vec_vblank
-00:c017 intr_vec_stat
-00:c01a round1
-00:c01b round2
-00:c01c round3

M cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/test.gb → cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/test.gb

M cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/test.sym → cinema/gb/mooneye-gb/acceptance/halt_ime0_ei/test.sym

@@ -1,206 +1,48 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime0_ei.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime0_ei.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
+00:0150 main
+00:0151 main@wait_ly_5
 00:0161 result_ime0
-00:0175 _wait_ly_5
-00:017b _wait_ly_6
-00:0191 _print_results_halt_1
-00:0194 _test_failure_cb_0
-00:019c _print_sl_data55
-00:01a2 _print_sl_out55
-00:01a5 result_ime1
-00:01b9 _wait_ly_7
-00:01bf _wait_ly_8
-00:01d5 _print_results_halt_2
-00:01d8 _test_ok_cb_0
-00:01e0 _print_sl_data56
-00:01e8 _print_sl_out56
+00:0168 result_ime0@quit_inline_1
+00:0177 result_ime1
+00:017e result_ime1@quit_inline_2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000011 _sizeof_main
+00000016 _sizeof_result_ime0

M cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/test.gb → cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/test.sym → cinema/gb/mooneye-gb/acceptance/halt_ime0_nointr_timing/test.sym

@@ -1,210 +1,135 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime0_nointr_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime0_nointr_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
 00:0167 test_round1
 00:0184 finish_round1
 00:0193 test_round2
 00:01af finish_round2
-00:01e2 fail_halt
-00:01f6 _wait_ly_5
-00:01fc _wait_ly_6
-00:0212 _print_results_halt_1
-00:0215 _test_failure_cb_0
-00:021d _print_sl_data55
-00:0228 _print_sl_out55
-00:022b fail_intr
-00:023f _wait_ly_7
-00:0245 _wait_ly_8
-00:025b _print_results_halt_2
-00:025e _test_failure_cb_1
-00:0266 _print_sl_data56
-00:0276 _print_sl_out56
+00:01e9 fail_halt
+00:01f0 fail_halt@quit_inline_1
+00:0204 fail_intr
+00:020b fail_intr@quit_inline_2
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000017 _sizeof_main
+0000001d _sizeof_test_round1
+0000000f _sizeof_finish_round1
+0000001c _sizeof_test_round2
+0000003a _sizeof_finish_round2
+0000001b _sizeof_fail_halt

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/test.gb → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/test.sym → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing/test.sym

@@ -1,198 +1,123 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0175 _wait_ly_4
-00:017b _wait_ly_5
-00:0191 _print_results_halt_1
-00:0194 _test_failure_cb_0
-00:019c _print_sl_data55
-00:01a8 _print_sl_out55
-00:01ab test_finish
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0168 main@quit_inline_1
+00:017d test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+0000002d _sizeof_main

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/test.gb → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/test.gb

M cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/test.sym → cinema/gb/mooneye-gb/acceptance/halt_ime1_timing2-GS/test.sym

@@ -1,195 +1,87 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing2-GS.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing2-GS.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
 00:0167 test_round1
 00:0183 _delay_long_time_0
 00:0193 finish_round1
@@ -200,38 +92,65 @@ 00:01dd test_round3
 00:01f8 finish_round3
 00:0207 test_round4
 00:0221 finish_round4
-00:0268 fail_halt
-00:027c _wait_ly_5
-00:0282 _wait_ly_6
-00:0298 _print_results_halt_1
-00:029b _test_failure_cb_0
-00:02a3 _print_sl_data55
-00:02ae _print_sl_out55
-00:02b1 fail_round1
-00:02c5 _wait_ly_7
-00:02cb _wait_ly_8
-00:02e1 _print_results_halt_2
-00:02e4 _test_failure_cb_1
-00:02ec _print_sl_data56
-00:02fa _print_sl_out56
-00:02fd fail_round2
-00:0311 _wait_ly_9
-00:0317 _wait_ly_10
-00:032d _print_results_halt_3
-00:0330 _test_failure_cb_2
-00:0338 _print_sl_data57
-00:0346 _print_sl_out57
-00:0349 fail_round3
-00:035d _wait_ly_11
-00:0363 _wait_ly_12
-00:0379 _print_results_halt_4
-00:037c _test_failure_cb_3
-00:0384 _print_sl_data58
-00:0392 _print_sl_out58
-00:0395 fail_round4
-00:03a9 _wait_ly_13
-00:03af _wait_ly_14
-00:03c5 _print_results_halt_5
-00:03c8 _test_failure_cb_4
-00:03d0 _print_sl_data59
-00:03de _print_sl_out59
+00:026d fail_halt
+00:0274 fail_halt@quit_inline_1
+00:0288 fail_round1
+00:028f fail_round1@quit_inline_2
+00:02a6 fail_round2
+00:02ad fail_round2@quit_inline_3
+00:02c4 fail_round3
+00:02cb fail_round3@quit_inline_4
+00:02e2 fail_round4
+00:02e9 fail_round4@quit_inline_5
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000017 _sizeof_main
+0000001c _sizeof_test_round1
+00000010 _sizeof__delay_long_time_0
+0000000f _sizeof_finish_round1
+0000001b _sizeof_test_round2
+00000011 _sizeof__delay_long_time_1
+0000000f _sizeof_finish_round2
+0000001b _sizeof_test_round3
+0000000f _sizeof_finish_round3
+0000001a _sizeof_test_round4
+0000004c _sizeof_finish_round4
+0000001b _sizeof_fail_halt
+0000001e _sizeof_fail_round1
+0000001e _sizeof_fail_round2
+0000001e _sizeof_fail_round3

D cinema/gb/mooneye-gb/acceptance/hdma_lcdc/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/hdma_lcdc/manifest.yml → cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/manifest.yml

@@ -1,2 +1,3 @@
 config:
   gb.model: CGB
+fail: true

M cinema/gb/mooneye-gb/acceptance/hdma_lcdc/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode3_timing/test.gb

D cinema/gb/mooneye-gb/acceptance/hdma_lcdc/test.sym

@@ -1,195 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/hdma_lcdc.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0154 test
-00:0161 test_finish
-00:017f _wait_ly_4
-00:0185 _wait_ly_5

M cinema/gb/mooneye-gb/acceptance/if_ie_registers/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/if_ie_registers/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/if_ie_registers/test.gb → cinema/gb/mooneye-gb/acceptance/if_ie_registers/test.gb

M cinema/gb/mooneye-gb/acceptance/if_ie_registers/test.sym → cinema/gb/mooneye-gb/acceptance/if_ie_registers/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/if_ie_registers.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/if_ie_registers.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:01ef test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+0000009f _sizeof_main

A cinema/gb/mooneye-gb/acceptance/instr/daa/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/instr/daa/test.gb

A cinema/gb/mooneye-gb/acceptance/instr/daa/test.sym

@@ -0,0 +1,59 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/instr/daa.gb".
+
+[labels]
+01:68ee clear_vram
+01:68ad disable_lcd_safe
+01:68b3 disable_lcd_safe@wait_ly_0
+01:6902 memcpy
+01:690b memset
+01:6866 print_bin4
+01:68cb print_hex4
+01:68f8 print_hex8
+01:691b print_inline_string
+01:68d7 print_load_font
+01:68e3 print_newline
+01:6914 print_string
+01:67f0 quit
+01:6805 quit@cb_return
+01:680a quit@wait_ly_1
+01:6810 quit@wait_ly_2
+01:6816 quit@wait_ly_3
+01:681c quit@wait_ly_4
+01:6826 quit@success
+01:684d quit@failure
+01:6862 quit@halt
+01:6863 quit@halt_execution_0
+01:6899 reset_screen
+01:68bc serial_send_byte
+01:6000 font
+00:0150 main
+00:0163 main@quit_inline_1
+00:0174 run_tests
+00:01a9 fail
+00:0274 fail@wait_ly_5
+00:027a fail@wait_ly_6
+00:0281 fail@halt_execution_1
+00:0284 testcases1
+01:4000 testcases2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000033 _sizeof_print_bin4
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00002000 _sizeof_testcases1
+00002000 _sizeof_testcases2
+00000024 _sizeof_main
+00000035 _sizeof_run_tests

M cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/test.gb → cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/test.gb

M cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/test.sym → cinema/gb/mooneye-gb/acceptance/interrupts/ie_push/test.sym

@@ -1,194 +1,30 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/interrupts/ie_push.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/interrupts/ie_push.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0200 round1
 00:0214 finish_round1
 00:021d round2
@@ -197,86 +33,59 @@ 00:0235 target
 00:0238 finish_round3
 00:023f round4
 00:0253 finish_round4
-00:0270 _wait_ly_4
-00:0276 _wait_ly_5
-00:028c _print_results_halt_1
-00:028f _test_ok_cb_0
-00:0297 _print_sl_data55
-00:029f _print_sl_out55
+00:0263 finish_round4@quit_inline_1
 00:1000 fail_round1_nointr
-00:1017 _wait_ly_6
-00:101d _wait_ly_7
-00:1033 _print_results_halt_2
-00:1036 _test_failure_cb_0
-00:103e _print_sl_data56
-00:104f _print_sl_out56
-00:1052 fail_round1_nocancel
-00:1069 _wait_ly_8
-00:106f _wait_ly_9
-00:1085 _print_results_halt_3
-00:1088 _test_failure_cb_1
-00:1090 _print_sl_data57
-00:10a2 _print_sl_out57
-00:10a5 fail_round1_if
-00:10bc _wait_ly_10
-00:10c2 _wait_ly_11
-00:10d8 _print_results_halt_4
-00:10db _test_failure_cb_2
-00:10e3 _print_sl_data58
-00:10f3 _print_sl_out58
-00:10f6 fail_round2_intr
-00:110d _wait_ly_12
-00:1113 _wait_ly_13
-00:1129 _print_results_halt_5
-00:112c _test_failure_cb_3
-00:1134 _print_sl_data59
-00:1146 _print_sl_out59
-00:1149 fail_round3_nointr
-00:1160 _wait_ly_14
-00:1166 _wait_ly_15
-00:117c _print_results_halt_6
-00:117f _test_failure_cb_4
-00:1187 _print_sl_data60
-00:1198 _print_sl_out60
-00:119b fail_round3_cancel
-00:11b2 _wait_ly_16
-00:11b8 _wait_ly_17
-00:11ce _print_results_halt_7
-00:11d1 _test_failure_cb_5
-00:11d9 _print_sl_data61
-00:11ed _print_sl_out61
-00:11f0 fail_round3_if
-00:1207 _wait_ly_18
-00:120d _wait_ly_19
-00:1223 _print_results_halt_8
-00:1226 _test_failure_cb_6
-00:122e _print_sl_data62
-00:123e _print_sl_out62
-00:1241 fail_round4_nointr
-00:1258 _wait_ly_20
-00:125e _wait_ly_21
-00:1274 _print_results_halt_9
-00:1277 _test_failure_cb_7
-00:127f _print_sl_data63
-00:1290 _print_sl_out63
-00:1293 fail_round4_cancel
-00:12aa _wait_ly_22
-00:12b0 _wait_ly_23
-00:12c6 _print_results_halt_10
-00:12c9 _test_failure_cb_8
-00:12d1 _print_sl_data64
-00:12e5 _print_sl_out64
-00:12e8 fail_round4_if
-00:12ff _wait_ly_24
-00:1305 _wait_ly_25
-00:131b _print_results_halt_11
-00:131e _test_failure_cb_9
-00:1326 _print_sl_data65
-00:1333 _print_sl_out65
-00:1336 fail_round4_vblank
-00:134d _wait_ly_26
-00:1353 _wait_ly_27
-00:1369 _print_results_halt_12
-00:136c _test_failure_cb_10
-00:1374 _print_sl_data66
-00:1383 _print_sl_out66
+00:100a fail_round1_nointr@quit_inline_2
+00:1024 fail_round1_nocancel
+00:102e fail_round1_nocancel@quit_inline_3
+00:1049 fail_round1_if
+00:1053 fail_round1_if@quit_inline_4
+00:106c fail_round2_intr
+00:1076 fail_round2_intr@quit_inline_5
+00:1091 fail_round3_nointr
+00:109b fail_round3_nointr@quit_inline_6
+00:10b5 fail_round3_cancel
+00:10bf fail_round3_cancel@quit_inline_7
+00:10dc fail_round3_if
+00:10e6 fail_round3_if@quit_inline_8
+00:10ff fail_round4_nointr
+00:1109 fail_round4_nointr@quit_inline_9
+00:1123 fail_round4_cancel
+00:112d fail_round4_cancel@quit_inline_10
+00:114a fail_round4_if
+00:1154 fail_round4_if@quit_inline_11
+00:116a fail_round4_vblank
+00:1174 fail_round4_vblank@quit_inline_12
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+000000b0 _sizeof_main
+00000014 _sizeof_round1
+00000009 _sizeof_finish_round1
+00000007 _sizeof_round2
+00000011 _sizeof_round3
+00000003 _sizeof_target
+00000007 _sizeof_finish_round3
+00000014 _sizeof_round4
+00000dad _sizeof_finish_round4
+00000024 _sizeof_fail_round1_nointr
+00000025 _sizeof_fail_round1_nocancel
+00000023 _sizeof_fail_round1_if
+00000025 _sizeof_fail_round2_intr
+00000024 _sizeof_fail_round3_nointr
+00000027 _sizeof_fail_round3_cancel
+00000023 _sizeof_fail_round3_if
+00000024 _sizeof_fail_round4_nointr
+00000027 _sizeof_fail_round4_cancel
+00000020 _sizeof_fail_round4_if

M cinema/gb/mooneye-gb/acceptance/intr_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/intr_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/intr_timing/test.gb → cinema/gb/mooneye-gb/acceptance/intr_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym → cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym

@@ -1,208 +1,132 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/intr_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/intr_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0157 test_round1
-00:01a7 _wait_ly_4
-00:01ad _wait_ly_5
-00:01c3 _print_results_halt_1
-00:01c6 _test_failure_cb_0
-00:01ce _print_sl_data55
-00:01dc _print_sl_out55
-00:01df finish_round1
-00:01e1 test_round2
-00:0232 _wait_ly_6
-00:0238 _wait_ly_7
-00:024e _print_results_halt_2
-00:0251 _test_failure_cb_1
-00:0259 _print_sl_data56
-00:0267 _print_sl_out56
-00:026a finish_round2
-00:026f test_finish
+00:019a test_round1@quit_inline_1
+00:01b1 finish_round1
+00:01b3 test_round2
+00:01f7 test_round2@quit_inline_2
+00:020e finish_round2
+00:0213 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000007 _sizeof_main
+0000005a _sizeof_test_round1
+00000002 _sizeof_finish_round1
+0000005b _sizeof_test_round2
+00000005 _sizeof_finish_round2

M cinema/gb/mooneye-gb/acceptance/jp_cc_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/jp_cc_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.gb → cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.sym → cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_cc_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_cc_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

M cinema/gb/mooneye-gb/acceptance/jp_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/jp_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/jp_timing/test.gb → cinema/gb/mooneye-gb/acceptance/jp_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/jp_timing/test.sym → cinema/gb/mooneye-gb/acceptance/jp_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

M cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/test.sym → cinema/gb/mooneye-gb/acceptance/ld_hl_sp_e_timing/test.sym

@@ -1,202 +1,136 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ld_hl_sp_e_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ld_hl_sp_e_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0187 test_finish
-00:01cb wram_test
-00:01d1 hiram_test
-00:01d3 _wait_ly_6
-00:01d9 _wait_ly_7
-00:01ee finish_round1
-00:01f0 _wait_ly_8
-00:01f6 _wait_ly_9
-00:020c finish_round2
+00:01d0 wram_test
+00:01d6 hiram_test
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+00:01de hiram_test@wait_ly_8
+00:01f3 finish_round1
+00:01f5 finish_round1@wait_ly_9
+00:01fb finish_round1@wait_ly_10
+00:0211 finish_round2
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000037 _sizeof_main
+00000049 _sizeof_test_finish
+00000006 _sizeof_wram_test
+0000001d _sizeof_hiram_test
+0000001e _sizeof_finish_round1

A cinema/gb/mooneye-gb/acceptance/oam_dma/basic/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/oam_dma/basic/test.sym

@@ -0,0 +1,63 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma/basic.gb".
+
+[labels]
+01:48c9 clear_oam
+01:48d3 clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:4898 memcmp
+01:48e7 memcpy
+01:48f0 memset
+01:48a6 print_hex4
+01:48dd print_hex8
+01:4900 print_inline_string
+01:48b2 print_load_font
+01:48be print_newline
+01:48f9 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:0176 fail
+00:0180 fail@quit_inline_1
+00:0195 finish
+00:019c finish@quit_inline_2
+00:01ad hiram_proc
+00:01b5 hiram_proc_end
+00:1200 random_data
+00:ff80 fail_offset
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+0000000e _sizeof_memcmp
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000001 _sizeof_fail_offset
+00000026 _sizeof_main
+0000001f _sizeof_fail
+00000018 _sizeof_finish
+00000008 _sizeof_hiram_proc
+0000104b _sizeof_hiram_proc_end

A cinema/gb/mooneye-gb/acceptance/oam_dma/reg_read/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/oam_dma/reg_read/test.sym

@@ -0,0 +1,92 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma/reg_read.gb".
+
+[labels]
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:0153 prepare_part1
+00:015f round1
+00:016b round2
+00:0177 prepare_part2
+00:0183 round3
+00:018d round4
+00:0197 prepare_part3
+00:01a3 round5
+00:01af round6
+00:01bb finish
+00:01c2 finish@quit_inline_1
+00:01d3 fail_round1
+00:01da fail_round1@quit_inline_2
+00:01ec fail_round2
+00:01f3 fail_round2@quit_inline_3
+00:0205 fail_round3
+00:020c fail_round3@quit_inline_4
+00:021e fail_round4
+00:0225 fail_round4@quit_inline_5
+00:0237 fail_round5
+00:023e fail_round5@quit_inline_6
+00:0250 fail_round6
+00:0257 fail_round6@quit_inline_7
+00:0269 hiram_proc1
+00:0271 hiram_proc1_end
+00:0271 hiram_proc2
+00:027b hiram_proc2_end
+00:027b hiram_proc3
+00:0286 hiram_proc3_end
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
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+0000000c _sizeof_prepare_part1
+0000000c _sizeof_round1
+0000000c _sizeof_round2
+0000000c _sizeof_prepare_part2
+0000000a _sizeof_round3
+0000000a _sizeof_round4
+0000000c _sizeof_prepare_part3
+0000000c _sizeof_round5
+0000000c _sizeof_round6
+00000018 _sizeof_finish
+00000019 _sizeof_fail_round1
+00000019 _sizeof_fail_round2
+00000019 _sizeof_fail_round3
+00000019 _sizeof_fail_round4
+00000019 _sizeof_fail_round5
+00000019 _sizeof_fail_round6
+00000008 _sizeof_hiram_proc1
+00000000 _sizeof_hiram_proc1_end
+0000000a _sizeof_hiram_proc2
+00000000 _sizeof_hiram_proc2_end
+0000000b _sizeof_hiram_proc3

A cinema/gb/mooneye-gb/acceptance/oam_dma/sources-dmgABCmgbS/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/acceptance/oam_dma/sources-dmgABCmgbS/test.sym

@@ -0,0 +1,113 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma/sources-dmgABCmgbS.gb".
+
+[labels]
+01:495d clear_oam
+01:4967 clear_vram
+01:4971 clear_wram
+01:491a disable_lcd_safe
+01:4920 disable_lcd_safe@wait_ly_0
+01:4938 memcmp
+01:497b memcpy
+01:4984 memset
+01:4994 print_inline_string
+01:4946 print_load_font
+01:4952 print_newline
+01:498d print_string
+01:4890 quit
+01:48a5 quit@cb_return
+01:48aa quit@wait_ly_1
+01:48b0 quit@wait_ly_2
+01:48b6 quit@wait_ly_3
+01:48bc quit@wait_ly_4
+01:48c6 quit@success
+01:48ed quit@failure
+01:4902 quit@halt
+01:4903 quit@halt_execution_0
+01:4906 reset_screen
+01:4929 serial_send_byte
+01:40a0 font
+00:0150 main
+00:015c prepare_part1
+00:015f test_0000
+00:0174 test_0000@quit_inline_1
+00:0189 test_3f00
+00:019e test_3f00@quit_inline_2
+00:01b3 test_4000
+00:01c8 test_4000@quit_inline_3
+00:01dd test_7f00
+00:01f2 test_7f00@quit_inline_4
+00:0207 prepare_part2
+00:0213 test_8000
+00:0228 test_8000@quit_inline_5
+00:023d test_9f00
+00:0252 test_9f00@quit_inline_6
+00:0267 prepare_part3
+00:0285 test_a000
+00:029a test_a000@quit_inline_7
+00:02af test_bf00
+00:02c4 test_bf00@quit_inline_8
+00:02d9 prepare_part4
+00:02ef test_c000
+00:0304 test_c000@quit_inline_9
+00:0319 test_df00
+00:032e test_df00@quit_inline_10
+00:0343 test_e000
+00:0358 test_e000@quit_inline_11
+00:036d test_fe00
+00:0385 test_fe00@quit_inline_12
+00:039a test_ff00
+00:03af test_ff00@quit_inline_13
+00:03c4 test_finish
+00:03cb test_finish@quit_inline_14
+00:03dc check_oam
+00:03e5 dma_proc
+00:03ed dma_proc_end
+00:03ed copy_dma_proc
+00:03f9 copy_ram_pattern_1
+00:0402 ram_pattern_1
+00:04a2 copy_ram_pattern_2
+00:04ab ram_pattern_2
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000a _sizeof_clear_wram
+0000000f _sizeof_disable_lcd_safe
+0000000e _sizeof_memcmp
+00000009 _sizeof_memcpy
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+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
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+000007f0 _sizeof_font
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+0000000c _sizeof_prepare_part2
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+0000001e _sizeof_prepare_part3
+0000002a _sizeof_test_a000
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+00000016 _sizeof_prepare_part4
+0000002a _sizeof_test_c000
+0000002a _sizeof_test_df00
+0000002a _sizeof_test_e000
+0000002d _sizeof_test_fe00
+0000002a _sizeof_test_ff00
+00000018 _sizeof_test_finish
+00000009 _sizeof_check_oam
+00000008 _sizeof_dma_proc
+00000000 _sizeof_dma_proc_end
+0000000c _sizeof_copy_dma_proc
+00000009 _sizeof_copy_ram_pattern_1
+000000a0 _sizeof_ram_pattern_1
+00000009 _sizeof_copy_ram_pattern_2

M cinema/gb/mooneye-gb/acceptance/oam_dma_restart/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/oam_dma_restart/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/oam_dma_restart/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma_restart/test.gb

M cinema/gb/mooneye-gb/acceptance/oam_dma_restart/test.sym → cinema/gb/mooneye-gb/acceptance/oam_dma_restart/test.sym

@@ -1,199 +1,130 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_restart.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_restart.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
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+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
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-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0171 test_finish
-00:01a1 hiram_test
-00:01a6 _wait_ly_6
-00:01ac _wait_ly_7
-00:01c6 _wait_ly_8
-00:01cc _wait_ly_9
+00:01a8 hiram_test
+00:01ad hiram_test@wait_ly_7
+00:01b3 hiram_test@wait_ly_8
+00:01cd hiram_test@wait_ly_9
+00:01d3 hiram_test@wait_ly_10
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000021 _sizeof_main
+00000037 _sizeof_test_finish

M cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.gb

M cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.sym → cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.sym

@@ -1,218 +1,148 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_start.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_start.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:015f test_round1
-00:0186 _wait_ly_4
-00:018c _wait_ly_5
+00:0186 test_round1@wait_ly_5
+00:018c test_round1@wait_ly_6
 00:019c fail_round1
-00:01b0 _wait_ly_6
-00:01b6 _wait_ly_7
-00:01cc _print_results_halt_1
-00:01cf _test_failure_cb_0
-00:01d7 _print_sl_data55
-00:01ed _print_sl_out55
-00:01f0 finish_round1
-00:01fd test_round2
-00:022a _wait_ly_8
-00:0230 _wait_ly_9
-00:0240 fail_round2
-00:0254 _wait_ly_10
-00:025a _wait_ly_11
-00:0270 _print_results_halt_2
-00:0273 _test_failure_cb_1
-00:027b _print_sl_data56
-00:0291 _print_sl_out56
-00:0294 finish_round2
-00:0299 test_finish
-00:c014 vector_10
-00:c016 vector_38
-00:c018 round1_oam
-00:c019 round1_b
+00:01a3 fail_round1@quit_inline_1
+00:01c2 finish_round1
+00:01cf test_round2
+00:01fc test_round2@wait_ly_7
+00:0202 test_round2@wait_ly_8
+00:0212 fail_round2
+00:0219 fail_round2@quit_inline_2
+00:0238 finish_round2
+00:023d test_finish
+00:ff91 vector_10
+00:ff93 vector_38
+00:ff95 round1_oam
+00:ff96 round1_b
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_vector_10
+00000002 _sizeof_vector_38
+00000001 _sizeof_round1_oam
+00000001 _sizeof_round1_b
+0000000f _sizeof_main
+0000003d _sizeof_test_round1
+00000026 _sizeof_fail_round1
+0000000d _sizeof_finish_round1
+00000043 _sizeof_test_round2
+00000026 _sizeof_fail_round2
+00000005 _sizeof_finish_round2

M cinema/gb/mooneye-gb/acceptance/oam_dma_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/oam_dma_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.gb → cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.sym → cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.sym

@@ -1,199 +1,130 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0171 test_finish
-00:01a1 hiram_test
-00:01a6 _wait_ly_6
-00:01ac _wait_ly_7
-00:01bd _wait_ly_8
-00:01c3 _wait_ly_9
+00:01a8 hiram_test
+00:01ad hiram_test@wait_ly_7
+00:01b3 hiram_test@wait_ly_8
+00:01c4 hiram_test@wait_ly_9
+00:01ca hiram_test@wait_ly_10
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000021 _sizeof_main
+00000037 _sizeof_test_finish

M cinema/gb/mooneye-gb/acceptance/pop_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/pop_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/pop_timing/test.gb → cinema/gb/mooneye-gb/acceptance/pop_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/pop_timing/test.sym → cinema/gb/mooneye-gb/acceptance/pop_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/pop_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/pop_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:02ad test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+0000015d _sizeof_main

A cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.sym

@@ -0,0 +1,100 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/hblank_ly_scx_timing-GS.gb".
+
+[labels]
+01:4940 clear_vram
+01:48ff disable_lcd_safe
+01:4905 disable_lcd_safe@wait_ly_0
+01:4954 memcpy
+01:495d memset
+01:491d print_hex4
+01:494a print_hex8
+01:496d print_inline_string
+01:4929 print_load_font
+01:4935 print_newline
+01:47f0 print_reg_dump
+01:4966 print_string
+01:4875 quit
+01:488a quit@cb_return
+01:488f quit@wait_ly_1
+01:4895 quit@wait_ly_2
+01:489b quit@wait_ly_3
+01:48a1 quit@wait_ly_4
+01:48ab quit@success
+01:48d2 quit@failure
+01:48e7 quit@halt
+01:48e8 quit@halt_execution_0
+01:48eb reset_screen
+01:490e serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:0395 main@quit_inline_1
+00:03a6 test_fail
+00:03ce test_fail@quit_inline_2
+00:03fc standard_delay
+00:0414 setup_and_wait
+00:0414 setup_and_wait@wait_ly_7
+00:041a setup_and_wait@wait_ly_8
+00:042e fail_halt
+00:0435 fail_halt@quit_inline_3
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000256 _sizeof_main
+00000056 _sizeof_test_fail
+00000018 _sizeof_standard_delay
+0000001a _sizeof_setup_and_wait

A cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/test.sym

@@ -0,0 +1,130 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_1_2_timing-GS.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:01b2 setup_and_wait_mode1
+00:01b2 setup_and_wait_mode1@wait_ly_7
+00:01c5 setup_and_wait_mode2
+00:01d2 fail_halt
+00:01d9 fail_halt@quit_inline_1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000062 _sizeof_main
+00000013 _sizeof_setup_and_wait_mode1
+0000000d _sizeof_setup_and_wait_mode2

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_0_timing/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_0_timing/test.sym

@@ -0,0 +1,130 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_0_timing.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:01b0 setup_and_wait_mode2
+00:01b0 setup_and_wait_mode2@wait_ly_7
+00:01d3 setup_and_wait_mode0
+00:01e0 fail_halt
+00:01e7 fail_halt@quit_inline_1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000060 _sizeof_main
+00000023 _sizeof_setup_and_wait_mode2
+0000000d _sizeof_setup_and_wait_mode0

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing/test.sym

@@ -0,0 +1,128 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_mode0_timing.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:020e setup_and_wait_mode2
+00:020e setup_and_wait_mode2@wait_ly_7
+00:0231 fail_halt
+00:0238 fail_halt@quit_inline_1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+000000be _sizeof_main
+00000023 _sizeof_setup_and_wait_mode2

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing_sprites/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode0_timing_sprites/test.sym

@@ -0,0 +1,499 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_mode0_timing_sprites.gb".
+
+[labels]
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A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode3_timing/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_mode3_timing/test.sym

@@ -0,0 +1,128 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_mode3_timing.gb".
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+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:01bc setup_and_wait_mode2
+00:01bc setup_and_wait_mode2@wait_ly_7
+00:01df fail_halt
+00:01e6 fail_halt@quit_inline_1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+0000006c _sizeof_main
+00000023 _sizeof_setup_and_wait_mode2

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_oam_ok_timing/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_oam_ok_timing/test.gb

A cinema/gb/mooneye-gb/acceptance/ppu/intr_2_oam_ok_timing/test.sym

@@ -0,0 +1,130 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_oam_ok_timing.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_oam
+01:4b85 clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b99 memcpy
+01:4ba2 memset
+01:4b58 print_hex4
+01:4b8f print_hex8
+01:4bb2 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4bab print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
+00:0211 setup_and_wait_mode2
+00:0211 setup_and_wait_mode2@wait_ly_7
+00:0234 fail_halt
+00:023b fail_halt@quit_inline_1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+000000c1 _sizeof_main
+00000023 _sizeof_setup_and_wait_mode2

A cinema/gb/mooneye-gb/acceptance/ppu/lcdon_timing-dmgABCmgbS/test.sym

@@ -0,0 +1,103 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/lcdon_timing-dmgABCmgbS.gb".
+
+[labels]
+01:4d03 clear_oam
+01:4d0d clear_vram
+01:4cc2 disable_lcd_safe
+01:4cc8 disable_lcd_safe@wait_ly_0
+01:4d21 memcpy
+01:4d2a memset
+01:4ce0 print_hex4
+01:4d17 print_hex8
+01:4d3a print_inline_string
+01:4cec print_load_font
+01:4cf8 print_newline
+01:4d33 print_string
+01:4c38 quit
+01:4c4d quit@cb_return
+01:4c52 quit@wait_ly_1
+01:4c58 quit@wait_ly_2
+01:4c5e quit@wait_ly_3
+01:4c64 quit@wait_ly_4
+01:4c6e quit@success
+01:4c95 quit@failure
+01:4caa quit@halt
+01:4cab quit@halt_execution_0
+01:4cae reset_screen
+01:4cd1 serial_send_byte
+01:4000 font
+00:0150 main
+00:015a test_ly
+00:0166 test_stat_lyc0
+00:0175 test_stat_lyc1
+00:0185 test_oam_access
+00:0191 test_vram_access
+00:019d test_finish
+00:01a4 test_finish@quit_inline_1
+01:4ac9 cycle_counts
+01:4ae1 expect_ly
+01:4afc expect_stat_lyc0
+01:4b1f expect_stat_lyc1
+01:4b42 expect_oam_access
+01:4b65 expect_vram_access
+01:4b89 verify_results
+01:4ba0 verify_fail
+01:4bc1 verify_fail@quit_inline_2
+00:ff80 v_pass1_results
+00:ff88 v_pass2_results
+00:ff90 v_pass3_results
+00:ff98 v_fail_round
+00:ff99 v_fail_expect
+00:ff9a v_fail_actual
+00:ff9b v_fail_str
+00:ff9b v_fail_str_l
+00:ff9c v_fail_str_h
+01:47f0 test_passes
+01:47f0 test_pass1
+01:48e2 test_pass2
+01:49d5 test_pass3
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000018 _sizeof_cycle_counts
+0000001b _sizeof_expect_ly
+00000023 _sizeof_expect_stat_lyc0
+00000023 _sizeof_expect_stat_lyc1
+00000023 _sizeof_expect_oam_access
+00000024 _sizeof_expect_vram_access
+00000017 _sizeof_verify_results
+00000098 _sizeof_verify_fail
+00000008 _sizeof_v_pass1_results
+00000008 _sizeof_v_pass2_results
+00000008 _sizeof_v_pass3_results
+00000001 _sizeof_v_fail_round
+00000001 _sizeof_v_fail_expect
+00000001 _sizeof_v_fail_actual
+00000002 _sizeof_v_fail_str
+00000001 _sizeof_v_fail_str_l
+00000001 _sizeof_v_fail_str_h
+00000000 _sizeof_test_passes
+000000f2 _sizeof_test_pass1
+000000f3 _sizeof_test_pass2
+000000f4 _sizeof_test_pass3
+0000000a _sizeof_main
+0000000c _sizeof_test_ly
+0000000f _sizeof_test_stat_lyc0
+00000010 _sizeof_test_stat_lyc1
+0000000c _sizeof_test_oam_access
+0000000c _sizeof_test_vram_access

A cinema/gb/mooneye-gb/acceptance/ppu/lcdon_write_timing-GS/test.gb

A cinema/gb/mooneye-gb/acceptance/ppu/lcdon_write_timing-GS/test.sym

@@ -0,0 +1,91 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/lcdon_write_timing-GS.gb".
+
+[labels]
+01:4a0b clear_oam
+01:4a15 clear_vram
+01:49ca disable_lcd_safe
+01:49d0 disable_lcd_safe@wait_ly_0
+01:4a29 memcpy
+01:4a32 memset
+01:49e8 print_hex4
+01:4a1f print_hex8
+01:4a42 print_inline_string
+01:49f4 print_load_font
+01:4a00 print_newline
+01:4a3b print_string
+01:48ed quit
+01:4902 quit@cb_return
+01:4907 quit@wait_ly_1
+01:490d quit@wait_ly_2
+01:4913 quit@wait_ly_3
+01:4919 quit@wait_ly_4
+01:4923 quit@success
+01:494a quit@failure
+01:495f quit@halt
+01:4960 quit@halt_execution_0
+01:49b6 reset_screen
+01:49d9 serial_send_byte
+01:4000 font
+00:0150 main
+00:015a test_oam_access
+00:0166 test_vram_access
+00:0172 test_finish
+00:0179 test_finish@quit_inline_1
+01:47f0 nop_counts
+01:4803 expect_oam_access
+01:4820 expect_vram_access
+01:483e verify_results
+01:4855 verify_fail
+01:4876 verify_fail@quit_inline_2
+00:c000 v_test_code
+00:c12c v_test_results
+00:ff80 v_fail_round
+00:ff81 v_fail_expect
+00:ff82 v_fail_actual
+00:ff83 v_fail_str
+00:ff83 v_fail_str_l
+00:ff84 v_fail_str_h
+01:4963 run_tests
+01:497c test_case
+01:49b0 test_case_prologue
+01:49b4 test_case_epilogue
+01:49b6 test_case_end
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000013 _sizeof_nop_counts
+0000001d _sizeof_expect_oam_access
+0000001e _sizeof_expect_vram_access
+00000017 _sizeof_verify_results
+00000098 _sizeof_verify_fail
+0000012c _sizeof_v_test_code
+00000013 _sizeof_v_test_results
+00000001 _sizeof_v_fail_round
+00000001 _sizeof_v_fail_expect
+00000001 _sizeof_v_fail_actual
+00000002 _sizeof_v_fail_str
+00000001 _sizeof_v_fail_str_l
+00000001 _sizeof_v_fail_str_h
+00000019 _sizeof_run_tests
+00000034 _sizeof_test_case
+00000004 _sizeof_test_case_prologue
+00000002 _sizeof_test_case_epilogue
+00000000 _sizeof_test_case_end
+0000000a _sizeof_main
+0000000c _sizeof_test_oam_access
+0000000c _sizeof_test_vram_access

A cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/test.gb

A cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/test.sym

@@ -0,0 +1,102 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/stat_irq_blocking.gb".
+
+[labels]
+01:4940 clear_vram
+01:48ff disable_lcd_safe
+01:4905 disable_lcd_safe@wait_ly_0
+01:4954 memcpy
+01:495d memset
+01:491d print_hex4
+01:494a print_hex8
+01:496d print_inline_string
+01:4929 print_load_font
+01:4935 print_newline
+01:47f0 print_reg_dump
+01:4966 print_string
+01:4875 quit
+01:488a quit@cb_return
+01:488f quit@wait_ly_1
+01:4895 quit@wait_ly_2
+01:489b quit@wait_ly_3
+01:48a1 quit@wait_ly_4
+01:48ab quit@success
+01:48d2 quit@failure
+01:48e7 quit@halt
+01:48e8 quit@halt_execution_0
+01:48eb reset_screen
+01:490e serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 test_round1
+00:0156 test_round1@wait_ly_5
+00:015c test_round1@wait_ly_6
+00:016b fail_round1
+00:0173 fail_round1@quit_inline_1
+00:018e test_round2
+00:0198 ly_iteration
+00:01ae finish_round2
+00:01b6 finish_round2@quit_inline_2
+00:01c7 fail_round2
+00:01ec fail_round2@quit_inline_3
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000001 _sizeof_main
+0000001a _sizeof_test_round1
+00000023 _sizeof_fail_round1
+0000000a _sizeof_test_round2
+00000016 _sizeof_ly_iteration
+00000019 _sizeof_finish_round2

A cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/test.gb

A cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/test.sym

@@ -0,0 +1,80 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/stat_lyc_onoff.gb".
+
+[labels]
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:0158 round1
+00:015b round1@wait_ly_5
+00:0161 round1@wait_ly_6
+00:017f round1@quit_inline_1
+00:01a9 round1@quit_inline_2
+00:01d3 round1@quit_inline_3
+00:01ec round2
+00:01f0 round2@wait_ly_7
+00:01f6 round2@wait_ly_8
+00:0214 round2@quit_inline_4
+00:023e round2@quit_inline_5
+00:0268 round2@quit_inline_6
+00:0281 round3
+00:0285 round3@wait_ly_9
+00:028b round3@wait_ly_10
+00:02a7 round3@quit_inline_7
+00:02d1 round3@quit_inline_8
+00:02fb round3@quit_inline_9
+00:0314 round4
+00:0315 round4@wait_ly_11
+00:031b round4@wait_ly_12
+00:0337 round4@quit_inline_10
+00:035d round4@quit_inline_11
+00:0377 finish
+00:037e finish@quit_inline_12
+00:038f fail_intr_round1
+00:0396 fail_intr_round1@quit_inline_13
+00:03ad fail_intr_round2
+00:03b4 fail_intr_round2@quit_inline_14
+00:03cb fail_intr_round3
+00:03d2 fail_intr_round3@quit_inline_15
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_main
+00000094 _sizeof_round1
+00000095 _sizeof_round2
+00000093 _sizeof_round3
+00000063 _sizeof_round4
+00000018 _sizeof_finish
+0000001e _sizeof_fail_intr_round1
+0000001e _sizeof_fail_intr_round2

A cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/baseline_0000.png

A cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/test.gb

A cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/test.sym

@@ -0,0 +1,155 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/vblank_stat_intr-GS.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0169 fail_halt
+00:0170 fail_halt@quit_inline_1
+00:017e test_round1
+00:018a test_round1@wait_ly_5
+00:01d5 finish_round1
+00:01f3 test_round2
+00:01ff test_round2@wait_ly_6
+00:024b finish_round2
+00:026d test_round3
+00:0279 test_round3@wait_ly_7
+00:02c4 finish_round3
+00:02e2 test_round4
+00:02ee test_round4@wait_ly_8
+00:033a finish_round4
+00:033c test_finish
+00:ff91 intr_vec_vblank
+00:ff94 intr_vec_stat
+00:ff97 round1
+00:ff98 round2
+00:ff99 round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000003 _sizeof_intr_vec_vblank
+00000003 _sizeof_intr_vec_stat
+00000001 _sizeof_round1
+00000001 _sizeof_round2
+00000001 _sizeof_round3
+00000019 _sizeof_main
+00000015 _sizeof_fail_halt
+00000057 _sizeof_test_round1
+0000001e _sizeof_finish_round1
+00000058 _sizeof_test_round2
+00000022 _sizeof_finish_round2
+00000057 _sizeof_test_round3
+0000001e _sizeof_finish_round3
+00000058 _sizeof_test_round4
+00000002 _sizeof_finish_round4

M cinema/gb/mooneye-gb/acceptance/push_timing/test.gb → cinema/gb/mooneye-gb/acceptance/push_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/push_timing/test.sym → cinema/gb/mooneye-gb/acceptance/push_timing/test.sym

@@ -1,199 +1,130 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/push_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/push_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01bb hiram_test
-00:01c2 _wait_ly_6
-00:01c8 _wait_ly_7
-00:01e2 _wait_ly_8
-00:01e8 _wait_ly_9
+00:01c0 hiram_test
+00:01c7 hiram_test@wait_ly_7
+00:01cd hiram_test@wait_ly_8
+00:01e7 hiram_test@wait_ly_9
+00:01ed hiram_test@wait_ly_10
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+00000049 _sizeof_test_finish

M cinema/gb/mooneye-gb/acceptance/rapid_di_ei/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/rapid_di_ei/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/rapid_di_ei/test.gb → cinema/gb/mooneye-gb/acceptance/rapid_di_ei/test.gb

M cinema/gb/mooneye-gb/acceptance/rapid_di_ei/test.sym → cinema/gb/mooneye-gb/acceptance/rapid_di_ei/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/rapid_di_ei.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/rapid_di_ei.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:018b test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+0000003b _sizeof_main

M cinema/gb/mooneye-gb/acceptance/ret_cc_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/ret_cc_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.sym → cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.sym

@@ -1,223 +1,64 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_cc_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_cc_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:015c test_round1
-00:015c _wait_ly_4
-00:0162 _wait_ly_5
-00:017c _wait_ly_6
-00:0182 _wait_ly_7
+00:015c test_round1@wait_ly_5
+00:0162 test_round1@wait_ly_6
+00:017c test_round1@wait_ly_7
+00:0182 test_round1@wait_ly_8
 00:0192 finish_round1
-00:01a9 _wait_ly_8
-00:01af _wait_ly_9
-00:01c5 _print_results_halt_1
-00:01c8 _test_failure_cb_0
-00:01d0 _print_sl_data55
-00:01de _print_sl_out55
-00:01e1 test_round2
-00:01e1 _wait_ly_10
-00:01e7 _wait_ly_11
-00:01fb _wait_ly_12
-00:0201 _wait_ly_13
-00:0212 finish_round2
-00:0229 _wait_ly_14
-00:022f _wait_ly_15
-00:0245 _print_results_halt_2
-00:0248 _test_failure_cb_1
-00:0250 _print_sl_data56
-00:025e _print_sl_out56
-00:0261 test_success
-00:0275 _wait_ly_16
-00:027b _wait_ly_17
-00:0291 _print_results_halt_3
-00:0294 _test_ok_cb_0
-00:029c _print_sl_data57
-00:02a4 _print_sl_out57
-00:02a7 hiram_cb
+00:019c finish_round1@quit_inline_1
+00:01b3 test_round2
+00:01b3 test_round2@wait_ly_9
+00:01b9 test_round2@wait_ly_10
+00:01cd test_round2@wait_ly_11
+00:01d3 test_round2@wait_ly_12
+00:01e4 finish_round2
+00:01ee finish_round2@quit_inline_2
+00:0205 test_success
+00:020c test_success@quit_inline_3
+00:021d hiram_cb
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000000c _sizeof_main
+00000036 _sizeof_test_round1
+00000021 _sizeof_finish_round1
+00000031 _sizeof_test_round2
+00000021 _sizeof_finish_round2
+00000018 _sizeof_test_success

M cinema/gb/mooneye-gb/acceptance/ret_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/ret_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/ret_timing/test.gb → cinema/gb/mooneye-gb/acceptance/ret_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/ret_timing/test.sym → cinema/gb/mooneye-gb/acceptance/ret_timing/test.sym

@@ -1,223 +1,64 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:015c test_round1
-00:015c _wait_ly_4
-00:0162 _wait_ly_5
-00:017c _wait_ly_6
-00:0182 _wait_ly_7
+00:015c test_round1@wait_ly_5
+00:0162 test_round1@wait_ly_6
+00:017c test_round1@wait_ly_7
+00:0182 test_round1@wait_ly_8
 00:0193 finish_round1
-00:01aa _wait_ly_8
-00:01b0 _wait_ly_9
-00:01c6 _print_results_halt_1
-00:01c9 _test_failure_cb_0
-00:01d1 _print_sl_data55
-00:01df _print_sl_out55
-00:01e2 test_round2
-00:01e2 _wait_ly_10
-00:01e8 _wait_ly_11
-00:01fc _wait_ly_12
-00:0202 _wait_ly_13
-00:0214 finish_round2
-00:022b _wait_ly_14
-00:0231 _wait_ly_15
-00:0247 _print_results_halt_2
-00:024a _test_failure_cb_1
-00:0252 _print_sl_data56
-00:0260 _print_sl_out56
-00:0263 test_success
-00:0277 _wait_ly_16
-00:027d _wait_ly_17
-00:0293 _print_results_halt_3
-00:0296 _test_ok_cb_0
-00:029e _print_sl_data57
-00:02a6 _print_sl_out57
-00:02a9 hiram_cb
+00:019d finish_round1@quit_inline_1
+00:01b4 test_round2
+00:01b4 test_round2@wait_ly_9
+00:01ba test_round2@wait_ly_10
+00:01ce test_round2@wait_ly_11
+00:01d4 test_round2@wait_ly_12
+00:01e6 finish_round2
+00:01f0 finish_round2@quit_inline_2
+00:0207 test_success
+00:020e test_success@quit_inline_3
+00:021f hiram_cb
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000000c _sizeof_main
+00000037 _sizeof_test_round1
+00000021 _sizeof_finish_round1
+00000032 _sizeof_test_round2
+00000021 _sizeof_finish_round2
+00000018 _sizeof_test_success

M cinema/gb/mooneye-gb/acceptance/reti_intr_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/reti_intr_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/reti_intr_timing/test.gb → cinema/gb/mooneye-gb/acceptance/reti_intr_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/reti_intr_timing/test.sym → cinema/gb/mooneye-gb/acceptance/reti_intr_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_intr_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_intr_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0160 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000010 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/reti_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/reti_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/reti_timing/test.gb → cinema/gb/mooneye-gb/acceptance/reti_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/reti_timing/test.sym → cinema/gb/mooneye-gb/acceptance/reti_timing/test.sym

@@ -1,223 +1,64 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:015c test_round1
-00:015c _wait_ly_4
-00:0162 _wait_ly_5
-00:017c _wait_ly_6
-00:0182 _wait_ly_7
+00:015c test_round1@wait_ly_5
+00:0162 test_round1@wait_ly_6
+00:017c test_round1@wait_ly_7
+00:0182 test_round1@wait_ly_8
 00:0193 finish_round1
-00:01aa _wait_ly_8
-00:01b0 _wait_ly_9
-00:01c6 _print_results_halt_1
-00:01c9 _test_failure_cb_0
-00:01d1 _print_sl_data55
-00:01df _print_sl_out55
-00:01e2 test_round2
-00:01e2 _wait_ly_10
-00:01e8 _wait_ly_11
-00:01fc _wait_ly_12
-00:0202 _wait_ly_13
-00:0214 finish_round2
-00:022b _wait_ly_14
-00:0231 _wait_ly_15
-00:0247 _print_results_halt_2
-00:024a _test_failure_cb_1
-00:0252 _print_sl_data56
-00:0260 _print_sl_out56
-00:0263 test_success
-00:0277 _wait_ly_16
-00:027d _wait_ly_17
-00:0293 _print_results_halt_3
-00:0296 _test_ok_cb_0
-00:029e _print_sl_data57
-00:02a6 _print_sl_out57
-00:02a9 hiram_cb
+00:019d finish_round1@quit_inline_1
+00:01b4 test_round2
+00:01b4 test_round2@wait_ly_9
+00:01ba test_round2@wait_ly_10
+00:01ce test_round2@wait_ly_11
+00:01d4 test_round2@wait_ly_12
+00:01e6 finish_round2
+00:01f0 finish_round2@quit_inline_2
+00:0207 test_success
+00:020e test_success@quit_inline_3
+00:021f hiram_cb
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000000c _sizeof_main
+00000037 _sizeof_test_round1
+00000021 _sizeof_finish_round1
+00000032 _sizeof_test_round2
+00000021 _sizeof_finish_round2
+00000018 _sizeof_test_success

M cinema/gb/mooneye-gb/acceptance/rst_timing/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/rst_timing/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/rst_timing/test.gb → cinema/gb/mooneye-gb/acceptance/rst_timing/test.gb

M cinema/gb/mooneye-gb/acceptance/rst_timing/test.sym → cinema/gb/mooneye-gb/acceptance/rst_timing/test.sym

@@ -1,201 +1,134 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/rst_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/rst_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01bb hiram_test
-00:01be _wait_ly_6
-00:01c4 _wait_ly_7
-00:01d9 finish_round1
-00:01dc _wait_ly_8
-00:01e2 _wait_ly_9
-00:01f8 finish_round2
+00:01c0 hiram_test
+00:01c3 hiram_test@wait_ly_7
+00:01c9 hiram_test@wait_ly_8
+00:01de finish_round1
+00:01e1 finish_round1@wait_ly_9
+00:01e7 finish_round1@wait_ly_10
+00:01fd finish_round2
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+00000049 _sizeof_test_finish
+0000001e _sizeof_hiram_test
+0000001f _sizeof_finish_round1

M cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/manifest.yml → cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/manifest.yml

M cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.gb → cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/test.gb

D cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sav

D cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sym

@@ -1,198 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/serial/boot_sclk_align-dmgABCXmgb.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:3828 _wait_ly_4
-00:382e _wait_ly_5
-00:3844 _print_results_halt_1
-00:3847 _test_failure_cb_0
-00:384f _print_sl_data55
-00:385e _print_sl_out55
-00:3861 test_finish

A cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/test.sym

@@ -0,0 +1,123 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/serial/boot_sclk_align-dmgABCmgb.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:381b main@quit_inline_1
+00:3833 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+000036e3 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/timer/div_write/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/div_write/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/div_write/test.gb → cinema/gb/mooneye-gb/acceptance/timer/div_write/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/div_write/test.sym → cinema/gb/mooneye-gb/acceptance/timer/div_write/test.sym

@@ -1,205 +1,47 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/div_write.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/div_write.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0150 test
-00:0182 _wait_ly_4
-00:0188 _wait_ly_5
-00:019e _print_results_halt_1
-00:01a1 _test_ok_cb_0
-00:01a9 _print_sl_data55
-00:01b1 _print_sl_out55
-00:01b4 test_failure
-00:01c8 _wait_ly_6
-00:01ce _wait_ly_7
-00:01e4 _print_results_halt_2
-00:01e7 _test_failure_cb_0
-00:01ef _print_sl_data56
-00:01fa _print_sl_out56
+00:0175 test@quit_inline_1
+00:0186 quit_failure
+00:018d quit_failure@quit_inline_2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000000 _sizeof_test
+00000036 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.gb → cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.sym → cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/rapid_toggle.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/rapid_toggle.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
-00:0186 _wait_ly_4
-00:018c _wait_ly_5
-00:01a2 _print_results_halt_1
-00:01a5 _test_failure_cb_0
-00:01ad _print_sl_data55
-00:01bb _print_sl_out55
-00:01be test_finish
+00:0179 test@quit_inline_1
+00:0190 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test
+00000040 _sizeof_main

M cinema/gb/mooneye-gb/acceptance/timer/tim00/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim00/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim00/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim00/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim00/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim00/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim00.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim00.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim00_div_trigger.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim00_div_trigger.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim01/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim01/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim01/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim01/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim01/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim01/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim01.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim01.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim01_div_trigger/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim01_div_trigger.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim01_div_trigger.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim10/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim10/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim10/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim10/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10_div_trigger.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10_div_trigger.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim11/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim11/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim11/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim11/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim11/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim11/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim11.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim11.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tim11_div_trigger/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim11_div_trigger.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim11_div_trigger.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tima_reload/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tima_reload/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tima_reload/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tima_reload/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tima_reload/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tima_reload/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tima_reload.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tima_reload.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tima_write_reloading/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tima_write_reloading.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tima_write_reloading.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

M cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/baseline_0000.png → cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/baseline_0000.png

M cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/test.gb → cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/test.gb

M cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/test.sym → cinema/gb/mooneye-gb/acceptance/timer/tma_write_reloading/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tma_write_reloading.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tma_write_reloading.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0150 test
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000000 _sizeof_test

A cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.sym

@@ -0,0 +1,84 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/bits_ram_en.gb".
+
+[labels]
+01:48c9 clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:4898 memcmp
+01:48dd memcpy
+01:48e6 memset
+01:48a6 print_hex4
+01:48d3 print_hex8
+01:48f6 print_inline_string
+01:48b2 print_load_font
+01:48be print_newline
+01:48ef print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:0164 test_round1
+00:018e test_round2
+00:01ae test_round2@expect_enabled
+00:01b3 test_round2@expect_disabled
+00:01cc test_round2@quit_inline_1
+00:01dd ram_data_enabled
+00:01ed ram_data_disabled
+00:01fd compare_ram_data
+00:0206 fail_round1_disable
+00:020d fail_round1_disable@quit_inline_2
+00:0240 fail_round1_enable
+00:0247 fail_round1_enable@quit_inline_3
+00:0279 fail_round1_print_test_address
+00:0286 fail_round2_disable
+00:028d fail_round2_disable@quit_inline_4
+00:02ab fail_round2_expect
+00:02b2 fail_round2_expect@quit_inline_5
+00:2000 ram_en_expectations
+00:ff80 test_address
+00:ff80 test_address_l
+00:ff81 test_address_h
+00:ff82 ram_en_value
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+0000000e _sizeof_memcmp
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_test_address
+00000001 _sizeof_test_address_l
+00000001 _sizeof_test_address_h
+00000001 _sizeof_ram_en_value
+00000014 _sizeof_main
+0000002a _sizeof_test_round1
+0000004f _sizeof_test_round2
+00000010 _sizeof_ram_data_enabled
+00000010 _sizeof_ram_data_disabled
+00000009 _sizeof_compare_ram_data
+0000003a _sizeof_fail_round1_disable
+00000039 _sizeof_fail_round1_enable
+0000000d _sizeof_fail_round1_print_test_address
+00000025 _sizeof_fail_round2_disable
+00001d55 _sizeof_fail_round2_expect

M cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb".
 
 [labels]
-01:4001 print_load_font
-01:400e print_string
-01:4018 print_a
-01:4022 print_newline
-01:402d print_digit
-01:403a print_regs
-01:4043 _print_sl_data0
-01:4049 _print_sl_out0
-01:4056 _print_sl_data1
-01:405c _print_sl_out1
-01:406e _print_sl_data2
-01:4074 _print_sl_out2
-01:4081 _print_sl_data3
-01:4087 _print_sl_out3
-01:4099 _print_sl_data4
-01:409f _print_sl_out4
-01:40ac _print_sl_data5
-01:40b2 _print_sl_out5
-01:40c4 _print_sl_data6
-01:40ca _print_sl_out6
-01:40d7 _print_sl_data7
-01:40dd _print_sl_out7
+01:40cc clear_vram
+01:408b disable_lcd_safe
+01:4091 disable_lcd_safe@wait_ly_0
+01:40e0 memcpy
+01:40e9 memset
+01:40a9 print_hex4
+01:40d6 print_hex8
+01:40f9 print_inline_string
+01:40b5 print_load_font
+01:40c1 print_newline
+01:40f2 print_string
+01:4001 quit
+01:4016 quit@cb_return
+01:401b quit@wait_ly_1
+01:4021 quit@wait_ly_2
+01:4027 quit@wait_ly_3
+01:402d quit@wait_ly_4
+01:4037 quit@success
+01:405e quit@failure
+01:4073 quit@halt
+01:4074 quit@halt_execution_0
+01:4077 reset_screen
+01:409a serial_send_byte
 01:4134 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:4924 memcpy
-01:492d memset
-01:4936 memcmp
-01:4944 clear_vram
-01:494e clear_oam
-01:4958 disable_lcd_safe
-01:495e _wait_ly_0
-01:4964 _wait_ly_1
-01:496d reset_screen
-01:4981 process_results
-01:4995 _wait_ly_2
-01:499b _wait_ly_3
-01:49b1 _print_results_halt_0
-01:49b4 _process_results_cb
-01:49bf _print_sl_data8
-01:49c9 _print_sl_out8
-01:49e3 _print_sl_data9
-01:49ee _print_sl_out9
-01:4a06 _print_sl_data10
-01:4a12 _print_sl_out10
-01:4a13 dump_mem
-01:4a32 _dump_mem_line
-01:4a5c _check_asserts
-01:4a6a _print_sl_data11
-01:4a6d _print_sl_out11
-01:4a79 _print_sl_data12
-01:4a7b _print_sl_out12
-01:4a83 _print_sl_data13
-01:4a86 _print_sl_out13
-01:4a90 __check_assert_fail0
-01:4a9b _print_sl_data14
-01:4a9e _print_sl_out14
-01:4aa1 __check_assert_ok0
-01:4aa9 _print_sl_data15
-01:4aae _print_sl_out15
-01:4ab0 __check_assert_skip0
-01:4ab8 _print_sl_data16
-01:4ac0 _print_sl_out16
-01:4ac0 __check_assert_out0
-01:4acc _print_sl_data17
-01:4ace _print_sl_out17
-01:4ad6 _print_sl_data18
-01:4ad9 _print_sl_out18
-01:4ae3 __check_assert_fail1
-01:4aee _print_sl_data19
-01:4af1 _print_sl_out19
-01:4af4 __check_assert_ok1
-01:4afc _print_sl_data20
-01:4b01 _print_sl_out20
-01:4b03 __check_assert_skip1
-01:4b0b _print_sl_data21
-01:4b13 _print_sl_out21
-01:4b13 __check_assert_out1
-01:4b1e _print_sl_data22
-01:4b21 _print_sl_out22
-01:4b2d _print_sl_data23
-01:4b2f _print_sl_out23
-01:4b37 _print_sl_data24
-01:4b3a _print_sl_out24
-01:4b44 __check_assert_fail2
-01:4b4f _print_sl_data25
-01:4b52 _print_sl_out25
-01:4b55 __check_assert_ok2
-01:4b5d _print_sl_data26
-01:4b62 _print_sl_out26
-01:4b64 __check_assert_skip2
-01:4b6c _print_sl_data27
-01:4b74 _print_sl_out27
-01:4b74 __check_assert_out2
-01:4b80 _print_sl_data28
-01:4b82 _print_sl_out28
-01:4b8a _print_sl_data29
-01:4b8d _print_sl_out29
-01:4b97 __check_assert_fail3
-01:4ba2 _print_sl_data30
-01:4ba5 _print_sl_out30
-01:4ba8 __check_assert_ok3
-01:4bb0 _print_sl_data31
-01:4bb5 _print_sl_out31
-01:4bb7 __check_assert_skip3
-01:4bbf _print_sl_data32
-01:4bc7 _print_sl_out32
-01:4bc7 __check_assert_out3
-01:4bd2 _print_sl_data33
-01:4bd5 _print_sl_out33
-01:4be1 _print_sl_data34
-01:4be3 _print_sl_out34
-01:4beb _print_sl_data35
-01:4bee _print_sl_out35
-01:4bf8 __check_assert_fail4
-01:4c03 _print_sl_data36
-01:4c06 _print_sl_out36
-01:4c09 __check_assert_ok4
-01:4c11 _print_sl_data37
-01:4c16 _print_sl_out37
-01:4c18 __check_assert_skip4
-01:4c20 _print_sl_data38
-01:4c28 _print_sl_out38
-01:4c28 __check_assert_out4
-01:4c34 _print_sl_data39
-01:4c36 _print_sl_out39
-01:4c3e _print_sl_data40
-01:4c41 _print_sl_out40
-01:4c4b __check_assert_fail5
-01:4c56 _print_sl_data41
-01:4c59 _print_sl_out41
-01:4c5c __check_assert_ok5
-01:4c64 _print_sl_data42
-01:4c69 _print_sl_out42
-01:4c6b __check_assert_skip5
-01:4c73 _print_sl_data43
-01:4c7b _print_sl_out43
-01:4c7b __check_assert_out5
-01:4c86 _print_sl_data44
-01:4c89 _print_sl_out44
-01:4c95 _print_sl_data45
-01:4c97 _print_sl_out45
-01:4c9f _print_sl_data46
-01:4ca2 _print_sl_out46
-01:4cac __check_assert_fail6
-01:4cb7 _print_sl_data47
-01:4cba _print_sl_out47
-01:4cbd __check_assert_ok6
-01:4cc5 _print_sl_data48
-01:4cca _print_sl_out48
-01:4ccc __check_assert_skip6
-01:4cd4 _print_sl_data49
-01:4cdc _print_sl_out49
-01:4cdc __check_assert_out6
-01:4ce8 _print_sl_data50
-01:4cea _print_sl_out50
-01:4cf2 _print_sl_data51
-01:4cf5 _print_sl_out51
-01:4cff __check_assert_fail7
-01:4d0a _print_sl_data52
-01:4d0d _print_sl_out52
-01:4d10 __check_assert_ok7
-01:4d18 _print_sl_data53
-01:4d1d _print_sl_out53
-01:4d1f __check_assert_skip7
-01:4d27 _print_sl_data54
-01:4d2f _print_sl_out54
-01:4d2f __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_256Kb/test.sym

@@ -1,194 +1,31 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_256Kb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_256Kb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bd clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:4898 memcmp
+01:48c7 memcpy
+01:48d0 memset
+01:48e0 print_inline_string
+01:48a6 print_load_font
+01:48b2 print_newline
+01:48d9 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0150 test_round1
 00:016e test_round2
 00:01d2 test_round3
@@ -196,57 +33,56 @@ 00:0232 test_round4
 00:02a0 test_round5
 00:02fc test_round6
 00:0330 test_finish
-00:0347 _wait_ly_4
-00:034d _wait_ly_5
-00:0363 _print_results_halt_1
-00:0366 _test_ok_cb_0
-00:036e _print_sl_data55
-00:0376 _print_sl_out55
-00:0379 copy_bank_data
-00:0398 check_bank_data
-00:03b8 all_ff
-00:03c8 all_00
+00:033a test_finish@quit_inline_1
+00:034b copy_bank_data
+00:036a check_bank_data
+00:038a all_ff
+00:039a all_00
 00:1000 bank_data
 00:1040 clear_ram
 00:1062 fail_round1
-00:1079 _wait_ly_6
-00:107f _wait_ly_7
-00:1095 _print_results_halt_2
-00:1098 _test_failure_cb_0
-00:10a0 _print_sl_data56
-00:10ae _print_sl_out56
-00:10b1 fail_round2
-00:10c8 _wait_ly_8
-00:10ce _wait_ly_9
-00:10e4 _print_results_halt_3
-00:10e7 _test_failure_cb_1
-00:10ef _print_sl_data57
-00:10fd _print_sl_out57
-00:1100 fail_round3
-00:1117 _wait_ly_10
-00:111d _wait_ly_11
-00:1133 _print_results_halt_4
-00:1136 _test_failure_cb_2
-00:113e _print_sl_data58
-00:114c _print_sl_out58
-00:114f fail_round4
-00:1166 _wait_ly_12
-00:116c _wait_ly_13
-00:1182 _print_results_halt_5
-00:1185 _test_failure_cb_3
-00:118d _print_sl_data59
-00:119b _print_sl_out59
-00:119e fail_round5
-00:11b5 _wait_ly_14
-00:11bb _wait_ly_15
-00:11d1 _print_results_halt_6
-00:11d4 _test_failure_cb_4
-00:11dc _print_sl_data60
-00:11ea _print_sl_out60
-00:11ed fail_round6
-00:1204 _wait_ly_16
-00:120a _wait_ly_17
-00:1220 _print_results_halt_7
-00:1223 _test_failure_cb_5
-00:122b _print_sl_data61
-00:1239 _print_sl_out61
+00:106c fail_round1@quit_inline_2
+00:1083 fail_round2
+00:108d fail_round2@quit_inline_3
+00:10a4 fail_round3
+00:10ae fail_round3@quit_inline_4
+00:10c5 fail_round4
+00:10cf fail_round4@quit_inline_5
+00:10e6 fail_round5
+00:10f0 fail_round5@quit_inline_6
+00:1107 fail_round6
+00:1111 fail_round6@quit_inline_7
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+0000000e _sizeof_memcmp
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000000 _sizeof_test_round1
+0000001e _sizeof_main
+00000064 _sizeof_test_round2
+00000060 _sizeof_test_round3
+0000006e _sizeof_test_round4
+0000005c _sizeof_test_round5
+00000034 _sizeof_test_round6
+0000001b _sizeof_test_finish
+0000001f _sizeof_copy_bank_data
+00000020 _sizeof_check_bank_data
+00000010 _sizeof_all_ff
+00000c66 _sizeof_all_00
+00000040 _sizeof_bank_data
+00000022 _sizeof_clear_ram
+00000021 _sizeof_fail_round1
+00000021 _sizeof_fail_round2
+00000021 _sizeof_fail_round3
+00000021 _sizeof_fail_round4
+00000021 _sizeof_fail_round5

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/ram_64Kb/test.sym

@@ -1,244 +1,83 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_64Kb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_64Kb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bd clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:4898 memcmp
+01:48c7 memcpy
+01:48d0 memset
+01:48e0 print_inline_string
+01:48a6 print_load_font
+01:48b2 print_newline
+01:48d9 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0150 test_round1
 00:016e test_round2
 00:01c2 test_round3
 00:01cb test_round4
 00:01fb test_round5
 00:022c test_finish
-00:0243 _wait_ly_4
-00:0249 _wait_ly_5
-00:025f _print_results_halt_1
-00:0262 _test_ok_cb_0
-00:026a _print_sl_data55
-00:0272 _print_sl_out55
-00:0275 copy_bank_data
-00:028d check_bank_data
-00:02a6 all_ff
-00:02b6 all_00
+00:0236 test_finish@quit_inline_1
+00:0247 copy_bank_data
+00:025f check_bank_data
+00:0278 all_ff
+00:0288 all_00
 00:1000 bank_data
 00:1010 clear_ram
 00:1032 fail_round1
-00:1049 _wait_ly_6
-00:104f _wait_ly_7
-00:1065 _print_results_halt_2
-00:1068 _test_failure_cb_0
-00:1070 _print_sl_data56
-00:107e _print_sl_out56
-00:1081 fail_round2
-00:1098 _wait_ly_8
-00:109e _wait_ly_9
-00:10b4 _print_results_halt_3
-00:10b7 _test_failure_cb_1
-00:10bf _print_sl_data57
-00:10cd _print_sl_out57
-00:10d0 fail_round3
-00:10e7 _wait_ly_10
-00:10ed _wait_ly_11
-00:1103 _print_results_halt_4
-00:1106 _test_failure_cb_2
-00:110e _print_sl_data58
-00:111c _print_sl_out58
-00:111f fail_round4
-00:1136 _wait_ly_12
-00:113c _wait_ly_13
-00:1152 _print_results_halt_5
-00:1155 _test_failure_cb_3
-00:115d _print_sl_data59
-00:116b _print_sl_out59
-00:116e fail_round5
-00:1185 _wait_ly_14
-00:118b _wait_ly_15
-00:11a1 _print_results_halt_6
-00:11a4 _test_failure_cb_4
-00:11ac _print_sl_data60
-00:11ba _print_sl_out60
+00:103c fail_round1@quit_inline_2
+00:1053 fail_round2
+00:105d fail_round2@quit_inline_3
+00:1074 fail_round3
+00:107e fail_round3@quit_inline_4
+00:1095 fail_round4
+00:109f fail_round4@quit_inline_5
+00:10b6 fail_round5
+00:10c0 fail_round5@quit_inline_6
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+0000000e _sizeof_memcmp
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000000 _sizeof_test_round1
+0000001e _sizeof_main
+00000054 _sizeof_test_round2
+00000009 _sizeof_test_round3
+00000030 _sizeof_test_round4
+00000031 _sizeof_test_round5
+0000001b _sizeof_test_finish
+00000018 _sizeof_copy_bank_data
+00000019 _sizeof_check_bank_data
+00000010 _sizeof_all_ff
+00000d78 _sizeof_all_00
+00000010 _sizeof_bank_data
+00000022 _sizeof_clear_ram
+00000021 _sizeof_fail_round1
+00000021 _sizeof_fail_round2
+00000021 _sizeof_fail_round3
+00000021 _sizeof_fail_round4

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_16Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_16Mb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_1Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_1Mb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_2Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_2Mb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_4Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_4Mb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_512Kb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_512Kb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/baseline_0000.png → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.gb

M cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym → cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym

@@ -1,226 +1,69 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_8Mb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_8Mb.gb".
 
 [labels]
-01:4c00 print_load_font
-01:4c0d print_string
-01:4c17 print_a
-01:4c21 print_newline
-01:4c2c print_digit
-01:4c39 print_regs
-01:4c42 _print_sl_data0
-01:4c48 _print_sl_out0
-01:4c55 _print_sl_data1
-01:4c5b _print_sl_out1
-01:4c6d _print_sl_data2
-01:4c73 _print_sl_out2
-01:4c80 _print_sl_data3
-01:4c86 _print_sl_out3
-01:4c98 _print_sl_data4
-01:4c9e _print_sl_out4
-01:4cab _print_sl_data5
-01:4cb1 _print_sl_out5
-01:4cc3 _print_sl_data6
-01:4cc9 _print_sl_out6
-01:4cd6 _print_sl_data7
-01:4cdc _print_sl_out7
+01:48bc clear_vram
+01:487b disable_lcd_safe
+01:4881 disable_lcd_safe@wait_ly_0
+01:48d0 memcpy
+01:48d9 memset
+01:4899 print_hex4
+01:48c6 print_hex8
+01:48e9 print_inline_string
+01:48a5 print_load_font
+01:48b1 print_newline
+01:48e2 print_string
+01:47f1 quit
+01:4806 quit@cb_return
+01:480b quit@wait_ly_1
+01:4811 quit@wait_ly_2
+01:4817 quit@wait_ly_3
+01:481d quit@wait_ly_4
+01:4827 quit@success
+01:484e quit@failure
+01:4863 quit@halt
+01:4864 quit@halt_execution_0
+01:4867 reset_screen
+01:488a serial_send_byte
 01:4001 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f1 memcpy
-01:47fa memset
-01:4803 memcmp
-01:4811 clear_vram
-01:481b clear_oam
-01:4825 disable_lcd_safe
-01:482b _wait_ly_0
-01:4831 _wait_ly_1
-01:483a reset_screen
-01:484e process_results
-01:4862 _wait_ly_2
-01:4868 _wait_ly_3
-01:487e _print_results_halt_0
-01:4881 _process_results_cb
-01:488c _print_sl_data8
-01:4896 _print_sl_out8
-01:48b0 _print_sl_data9
-01:48bb _print_sl_out9
-01:48d3 _print_sl_data10
-01:48df _print_sl_out10
-01:48e0 dump_mem
-01:48ff _dump_mem_line
-01:4929 _check_asserts
-01:4937 _print_sl_data11
-01:493a _print_sl_out11
-01:4946 _print_sl_data12
-01:4948 _print_sl_out12
-01:4950 _print_sl_data13
-01:4953 _print_sl_out13
-01:495d __check_assert_fail0
-01:4968 _print_sl_data14
-01:496b _print_sl_out14
-01:496e __check_assert_ok0
-01:4976 _print_sl_data15
-01:497b _print_sl_out15
-01:497d __check_assert_skip0
-01:4985 _print_sl_data16
-01:498d _print_sl_out16
-01:498d __check_assert_out0
-01:4999 _print_sl_data17
-01:499b _print_sl_out17
-01:49a3 _print_sl_data18
-01:49a6 _print_sl_out18
-01:49b0 __check_assert_fail1
-01:49bb _print_sl_data19
-01:49be _print_sl_out19
-01:49c1 __check_assert_ok1
-01:49c9 _print_sl_data20
-01:49ce _print_sl_out20
-01:49d0 __check_assert_skip1
-01:49d8 _print_sl_data21
-01:49e0 _print_sl_out21
-01:49e0 __check_assert_out1
-01:49eb _print_sl_data22
-01:49ee _print_sl_out22
-01:49fa _print_sl_data23
-01:49fc _print_sl_out23
-01:4a04 _print_sl_data24
-01:4a07 _print_sl_out24
-01:4a11 __check_assert_fail2
-01:4a1c _print_sl_data25
-01:4a1f _print_sl_out25
-01:4a22 __check_assert_ok2
-01:4a2a _print_sl_data26
-01:4a2f _print_sl_out26
-01:4a31 __check_assert_skip2
-01:4a39 _print_sl_data27
-01:4a41 _print_sl_out27
-01:4a41 __check_assert_out2
-01:4a4d _print_sl_data28
-01:4a4f _print_sl_out28
-01:4a57 _print_sl_data29
-01:4a5a _print_sl_out29
-01:4a64 __check_assert_fail3
-01:4a6f _print_sl_data30
-01:4a72 _print_sl_out30
-01:4a75 __check_assert_ok3
-01:4a7d _print_sl_data31
-01:4a82 _print_sl_out31
-01:4a84 __check_assert_skip3
-01:4a8c _print_sl_data32
-01:4a94 _print_sl_out32
-01:4a94 __check_assert_out3
-01:4a9f _print_sl_data33
-01:4aa2 _print_sl_out33
-01:4aae _print_sl_data34
-01:4ab0 _print_sl_out34
-01:4ab8 _print_sl_data35
-01:4abb _print_sl_out35
-01:4ac5 __check_assert_fail4
-01:4ad0 _print_sl_data36
-01:4ad3 _print_sl_out36
-01:4ad6 __check_assert_ok4
-01:4ade _print_sl_data37
-01:4ae3 _print_sl_out37
-01:4ae5 __check_assert_skip4
-01:4aed _print_sl_data38
-01:4af5 _print_sl_out38
-01:4af5 __check_assert_out4
-01:4b01 _print_sl_data39
-01:4b03 _print_sl_out39
-01:4b0b _print_sl_data40
-01:4b0e _print_sl_out40
-01:4b18 __check_assert_fail5
-01:4b23 _print_sl_data41
-01:4b26 _print_sl_out41
-01:4b29 __check_assert_ok5
-01:4b31 _print_sl_data42
-01:4b36 _print_sl_out42
-01:4b38 __check_assert_skip5
-01:4b40 _print_sl_data43
-01:4b48 _print_sl_out43
-01:4b48 __check_assert_out5
-01:4b53 _print_sl_data44
-01:4b56 _print_sl_out44
-01:4b62 _print_sl_data45
-01:4b64 _print_sl_out45
-01:4b6c _print_sl_data46
-01:4b6f _print_sl_out46
-01:4b79 __check_assert_fail6
-01:4b84 _print_sl_data47
-01:4b87 _print_sl_out47
-01:4b8a __check_assert_ok6
-01:4b92 _print_sl_data48
-01:4b97 _print_sl_out48
-01:4b99 __check_assert_skip6
-01:4ba1 _print_sl_data49
-01:4ba9 _print_sl_out49
-01:4ba9 __check_assert_out6
-01:4bb5 _print_sl_data50
-01:4bb7 _print_sl_out50
-01:4bbf _print_sl_data51
-01:4bc2 _print_sl_out51
-01:4bcc __check_assert_fail7
-01:4bd7 _print_sl_data52
-01:4bda _print_sl_out52
-01:4bdd __check_assert_ok7
-01:4be5 _print_sl_data53
-01:4bea _print_sl_out53
-01:4bec __check_assert_skip7
-01:4bf4 _print_sl_data54
-01:4bfc _print_sl_out54
-01:4bfc __check_assert_out7
+00:0150 main
 00:016b fail
-00:017f _wait_ly_4
-00:0185 _wait_ly_5
-00:019b _print_results_halt_1
-00:019e _fail_cb
-00:01a6 _print_sl_data55
-00:01b2 _print_sl_out55
-00:01c2 _print_sl_data56
-00:01ce _print_sl_out56
-00:01d8 _print_sl_data57
-00:01e4 _print_sl_out57
-00:01ef _print_sl_data58
-00:01f5 _print_sl_out58
-00:0208 _print_sl_data59
-00:0215 _print_sl_out59
-00:0225 _print_sl_data60
-00:0232 _print_sl_out60
-00:0242 _print_sl_data61
-00:024f _print_sl_out61
-00:025a c000_functions_start
-00:025a run_test_suite
-00:0284 _wait_ly_6
-00:028a _wait_ly_7
-00:02a0 _print_results_halt_2
-00:02a3 _test_ok_cb_0
-00:02ab _print_sl_data62
-00:02b3 _print_sl_out62
-00:02b6 run_tests
-00:02c4 run_test_cases
-00:02d2 test_case
-00:02ef restore_mbc1
-00:02f8 switch_bank
-00:0309 fetch_expected_value
-00:0328 c000_functions_end
-00:0328 expected_banks
+00:0172 fail@quit_inline_1
+00:020b c000_functions_start
+00:020b run_test_suite
+00:0228 run_test_suite@quit_inline_2
+00:0239 run_tests
+00:0247 run_test_cases
+00:0255 test_case
+00:0272 restore_mbc1
+00:027b switch_bank
+00:028c fetch_expected_value
+00:02ab c000_functions_end
+00:02ab expected_banks
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000180 _sizeof_expected_banks
+0000001b _sizeof_main
+000000a0 _sizeof_fail
+00000000 _sizeof_c000_functions_start
+0000002e _sizeof_run_test_suite
+0000000e _sizeof_run_tests
+0000000e _sizeof_run_test_cases
+0000001d _sizeof_test_case
+00000009 _sizeof_restore_mbc1
+00000011 _sizeof_switch_bank
+0000001f _sizeof_fetch_expected_value

D cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/baseline_0000.png

M cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.gb → cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.gb

D cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.sym

@@ -1,205 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/emulator-only/mbc1_rom_4banks.gb".
-
-[labels]
-0001:4bf3 print_load_font
-0001:4c00 print_string
-0001:4c0a print_a
-0001:4c14 print_newline
-0001:4c1f print_digit
-0001:4c2c print_regs
-0001:4c35 _print_sl_data0
-0001:4c3b _print_sl_out0
-0001:4c48 _print_sl_data1
-0001:4c4e _print_sl_out1
-0001:4c60 _print_sl_data2
-0001:4c66 _print_sl_out2
-0001:4c73 _print_sl_data3
-0001:4c79 _print_sl_out3
-0001:4c8b _print_sl_data4
-0001:4c91 _print_sl_out4
-0001:4c9e _print_sl_data5
-0001:4ca4 _print_sl_out5
-0001:4cb6 _print_sl_data6
-0001:4cbc _print_sl_out6
-0001:4cc9 _print_sl_data7
-0001:4ccf _print_sl_out7
-0001:4001 font
-0000:c000 regs_save
-0000:c000 regs_save.f
-0000:c001 regs_save.a
-0000:c002 regs_save.c
-0000:c003 regs_save.b
-0000:c004 regs_save.e
-0000:c005 regs_save.d
-0000:c006 regs_save.l
-0000:c007 regs_save.h
-0000:c008 regs_flags
-0000:c009 regs_assert
-0000:c009 regs_assert.f
-0000:c00a regs_assert.a
-0000:c00b regs_assert.c
-0000:c00c regs_assert.b
-0000:c00d regs_assert.e
-0000:c00e regs_assert.d
-0000:c00f regs_assert.l
-0000:c010 regs_assert.h
-0000:c011 memdump_len
-0000:c012 memdump_addr
-0001:47f1 memcpy
-0001:47fa memset
-0001:4803 clear_vram
-0001:480e reset_screen
-0001:481b process_results
-0001:4820 _wait_ly_0
-0001:4826 _wait_ly_1
-0001:4842 _wait_ly_2
-0001:4848 _wait_ly_3
-0001:4861 _process_results_cb
-0001:486c _print_sl_data8
-0001:4876 _print_sl_out8
-0001:4890 _print_sl_data9
-0001:489b _print_sl_out9
-0001:48b3 _print_sl_data10
-0001:48bf _print_sl_out10
-0001:48c0 dump_mem
-0001:48d0 _wait_ly_4
-0001:48d6 _wait_ly_5
-0001:48f2 _dump_mem_line
-0001:491c _check_asserts
-0001:492a _print_sl_data11
-0001:492d _print_sl_out11
-0001:4939 _print_sl_data12
-0001:493b _print_sl_out12
-0001:4943 _print_sl_data13
-0001:4946 _print_sl_out13
-0001:4950 __check_assert_fail0
-0001:495b _print_sl_data14
-0001:495e _print_sl_out14
-0001:4961 __check_assert_ok0
-0001:4969 _print_sl_data15
-0001:496e _print_sl_out15
-0001:4970 __check_assert_skip0
-0001:4978 _print_sl_data16
-0001:4980 _print_sl_out16
-0001:4980 __check_assert_out0
-0001:498c _print_sl_data17
-0001:498e _print_sl_out17
-0001:4996 _print_sl_data18
-0001:4999 _print_sl_out18
-0001:49a3 __check_assert_fail1
-0001:49ae _print_sl_data19
-0001:49b1 _print_sl_out19
-0001:49b4 __check_assert_ok1
-0001:49bc _print_sl_data20
-0001:49c1 _print_sl_out20
-0001:49c3 __check_assert_skip1
-0001:49cb _print_sl_data21
-0001:49d3 _print_sl_out21
-0001:49d3 __check_assert_out1
-0001:49de _print_sl_data22
-0001:49e1 _print_sl_out22
-0001:49ed _print_sl_data23
-0001:49ef _print_sl_out23
-0001:49f7 _print_sl_data24
-0001:49fa _print_sl_out24
-0001:4a04 __check_assert_fail2
-0001:4a0f _print_sl_data25
-0001:4a12 _print_sl_out25
-0001:4a15 __check_assert_ok2
-0001:4a1d _print_sl_data26
-0001:4a22 _print_sl_out26
-0001:4a24 __check_assert_skip2
-0001:4a2c _print_sl_data27
-0001:4a34 _print_sl_out27
-0001:4a34 __check_assert_out2
-0001:4a40 _print_sl_data28
-0001:4a42 _print_sl_out28
-0001:4a4a _print_sl_data29
-0001:4a4d _print_sl_out29
-0001:4a57 __check_assert_fail3
-0001:4a62 _print_sl_data30
-0001:4a65 _print_sl_out30
-0001:4a68 __check_assert_ok3
-0001:4a70 _print_sl_data31
-0001:4a75 _print_sl_out31
-0001:4a77 __check_assert_skip3
-0001:4a7f _print_sl_data32
-0001:4a87 _print_sl_out32
-0001:4a87 __check_assert_out3
-0001:4a92 _print_sl_data33
-0001:4a95 _print_sl_out33
-0001:4aa1 _print_sl_data34
-0001:4aa3 _print_sl_out34
-0001:4aab _print_sl_data35
-0001:4aae _print_sl_out35
-0001:4ab8 __check_assert_fail4
-0001:4ac3 _print_sl_data36
-0001:4ac6 _print_sl_out36
-0001:4ac9 __check_assert_ok4
-0001:4ad1 _print_sl_data37
-0001:4ad6 _print_sl_out37
-0001:4ad8 __check_assert_skip4
-0001:4ae0 _print_sl_data38
-0001:4ae8 _print_sl_out38
-0001:4ae8 __check_assert_out4
-0001:4af4 _print_sl_data39
-0001:4af6 _print_sl_out39
-0001:4afe _print_sl_data40
-0001:4b01 _print_sl_out40
-0001:4b0b __check_assert_fail5
-0001:4b16 _print_sl_data41
-0001:4b19 _print_sl_out41
-0001:4b1c __check_assert_ok5
-0001:4b24 _print_sl_data42
-0001:4b29 _print_sl_out42
-0001:4b2b __check_assert_skip5
-0001:4b33 _print_sl_data43
-0001:4b3b _print_sl_out43
-0001:4b3b __check_assert_out5
-0001:4b46 _print_sl_data44
-0001:4b49 _print_sl_out44
-0001:4b55 _print_sl_data45
-0001:4b57 _print_sl_out45
-0001:4b5f _print_sl_data46
-0001:4b62 _print_sl_out46
-0001:4b6c __check_assert_fail6
-0001:4b77 _print_sl_data47
-0001:4b7a _print_sl_out47
-0001:4b7d __check_assert_ok6
-0001:4b85 _print_sl_data48
-0001:4b8a _print_sl_out48
-0001:4b8c __check_assert_skip6
-0001:4b94 _print_sl_data49
-0001:4b9c _print_sl_out49
-0001:4b9c __check_assert_out6
-0001:4ba8 _print_sl_data50
-0001:4baa _print_sl_out50
-0001:4bb2 _print_sl_data51
-0001:4bb5 _print_sl_out51
-0001:4bbf __check_assert_fail7
-0001:4bca _print_sl_data52
-0001:4bcd _print_sl_out52
-0001:4bd0 __check_assert_ok7
-0001:4bd8 _print_sl_data53
-0001:4bdd _print_sl_out53
-0001:4bdf __check_assert_skip7
-0001:4be7 _print_sl_data54
-0001:4bef _print_sl_out54
-0001:4bef __check_assert_out7
-0000:01c8 _wait_ly_6
-0000:01ce _wait_ly_7
-0000:01ea _wait_ly_8
-0000:01f0 _wait_ly_9
-0000:0209 _test_ok_cb_0
-0000:0211 _print_sl_data55
-0000:0219 _print_sl_out55
-0000:021c switch_bank
-0000:0225 test_mbc
-0000:0236 _wait_ly_10
-0000:023c _wait_ly_11
-0000:0258 _wait_ly_12
-0000:025e _wait_ly_13
-0000:0277 _test_failure_cb_0
-0000:027f _print_sl_data56
-0000:028b _print_sl_out56

M cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.gb → cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.gb

M cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym → cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym

@@ -1,200 +1,38 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/madness/mgb_oam_dma_halt_sprites.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/madness/mgb_oam_dma_halt_sprites.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:481f clear_oam
+01:4829 clear_vram
+01:4804 disable_lcd_safe
+01:480a disable_lcd_safe@wait_ly_0
+01:4833 memcpy
+01:483c memset
+01:4813 print_load_font
+01:47f0 reset_screen
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0199 _wait_ly_4
-00:019f _wait_ly_5
+00:0150 main
+00:0199 main@wait_ly_5
+00:019f main@wait_ly_6
 00:01b4 hiram_test
-00:01b9 _wait_ly_6
-00:01bf _wait_ly_7
+00:01b9 hiram_test@wait_ly_7
+00:01bf hiram_test@wait_ly_8
 00:01cc vram_checkerboard
 00:05cc vram_checkerboard_end
 00:05cc initial_data
 00:05d4 initial_data_end
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_load_font
+00000014 _sizeof_reset_screen
+000007f0 _sizeof_font
+00000064 _sizeof_main
+00000018 _sizeof_hiram_test
+00000400 _sizeof_vram_checkerboard
+00000000 _sizeof_vram_checkerboard_end
+00000008 _sizeof_initial_data

M cinema/gb/mooneye-gb/manual-only/sprite_priority/test.gb → cinema/gb/mooneye-gb/manual-only/sprite_priority/test.gb

M cinema/gb/mooneye-gb/manual-only/sprite_priority/test.sym → cinema/gb/mooneye-gb/manual-only/sprite_priority/test.sym

@@ -1,193 +1,33 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/manual-only/sprite_priority.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/manual-only/sprite_priority.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:481f clear_oam
+01:4829 clear_vram
+01:4804 disable_lcd_safe
+01:480a disable_lcd_safe@wait_ly_0
+01:4833 memcpy
+01:483c memset
+01:4813 print_load_font
+01:47f0 reset_screen
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0180 data
-00:0214 data_end
+00:0150 main
+00:017d main@wait_ly_5
+00:0183 main@wait_ly_6
+00:0189 main@wait_ly_7
+00:018f main@wait_ly_8
+00:0196 main@halt_execution_1
+00:0199 data
+00:022d data_end
+
+[definitions]
+0000000a _sizeof_clear_oam
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_load_font
+00000014 _sizeof_reset_screen
+000007f0 _sizeof_font
+00000049 _sizeof_main
+00000094 _sizeof_data

M cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/baseline_0000.png → cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/baseline_0000.png

M cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/test.gb → cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/test.gb

M cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/test.sym → cinema/gb/mooneye-gb/misc/bits/unused_hwio-C/test.sym

@@ -1,194 +1,32 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/bits/unused_hwio-C.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/bits/unused_hwio-C.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c017 regs_save
-00:c017 regs_save.f
-00:c018 regs_save.a
-00:c019 regs_save.c
-00:c01a regs_save.b
-00:c01b regs_save.e
-00:c01c regs_save.d
-00:c01d regs_save.l
-00:c01e regs_save.h
-00:c01f regs_flags
-00:c020 regs_assert
-00:c020 regs_assert.f
-00:c021 regs_assert.a
-00:c022 regs_assert.c
-00:c023 regs_assert.b
-00:c024 regs_assert.e
-00:c025 regs_assert.d
-00:c026 regs_assert.l
-00:c027 regs_assert.h
-00:c028 memdump_len
-00:c029 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0161 _test_data_0
 00:0177 _finish_0
 00:0187 _test_data_1
@@ -497,39 +335,357 @@ 00:17f1 _test_data_152
 00:1807 _finish_152
 00:1817 _test_data_153
 00:182d _finish_153
-00:1841 _wait_ly_4
-00:1847 _wait_ly_5
-00:185d _print_results_halt_1
-00:1860 _test_ok_cb_0
-00:1868 _print_sl_data55
-00:1870 _print_sl_out55
-00:1873 run_testcase
-00:189e _wait_ly_6
-00:18a4 _wait_ly_7
-00:18ba _print_results_halt_2
-00:18bd test_failure_cb
-00:18c5 _print_sl_data56
-00:18d1 _print_sl_out56
-00:18df _print_sl_data57
-00:18e3 _print_sl_out57
-00:18f1 _print_sl_data58
-00:1901 _print_sl_out58
-00:190f _print_sl_data59
-00:191c _print_sl_out59
-00:192d _print_sl_data60
-00:193a _print_sl_out60
-00:194b _print_sl_data61
-00:1958 _print_sl_out61
-00:195e fetch_test_data
-00:1978 print_got
-00:198a _print_zero
-00:198e _print_one
-00:1990 _print_bit
-00:1999 _skip
-00:199a _next
-00:c000 test_addr
-00:c002 test_got
-00:c003 test_reg
-00:c004 test_mask
-00:c005 test_str_write
-00:c00e test_str_expect
+00:1834 _finish_153@quit_inline_1
+00:1845 run_testcase
+00:1863 run_testcase@quit_inline_2
+00:18e6 fetch_test_data
+00:1900 print_got
+00:1912 _print_zero
+00:1916 _print_one
+00:1918 _print_bit
+00:1921 _skip
+00:1922 _next
+00:ff80 test_addr
+00:ff82 test_got
+00:ff83 test_reg
+00:ff84 test_mask
+00:ff85 test_str_write
+00:ff8e test_str_expect
+
+[definitions]
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+0000000f _sizeof_disable_lcd_safe
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A cinema/gb/mooneye-gb/misc/boot_div-A/manifest.yml

@@ -0,0 +1,3 @@
+config:
+  gb.model: AGB
+fail: true

A cinema/gb/mooneye-gb/misc/boot_div-A/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_div-A.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
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+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
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+01:48e9 check_asserts_cb@ok2
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+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
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+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
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+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

A cinema/gb/mooneye-gb/misc/boot_div-cgb0/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.gb

A cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_div-cgb0.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

A cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/manifest.yml

@@ -0,0 +1,1 @@
+fail: true

A cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_div-cgbABCDE.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

M cinema/gb/mooneye-gb/misc/boot_hwio-C/baseline_0000.png → cinema/gb/mooneye-gb/misc/boot_hwio-C/baseline_0000.png

M cinema/gb/mooneye-gb/misc/boot_hwio-C/test.gb → cinema/gb/mooneye-gb/misc/boot_hwio-C/test.gb

M cinema/gb/mooneye-gb/misc/boot_hwio-C/test.sym → cinema/gb/mooneye-gb/misc/boot_hwio-C/test.sym

@@ -1,212 +1,57 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/boot_hwio-C.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_hwio-C.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01db _wait_ly_4
-00:01e1 _wait_ly_5
-00:01f7 _print_results_halt_1
-00:01fa _test_ok_cb_0
-00:0202 _print_sl_data55
-00:020a _print_sl_out55
-00:020d mismatch
-00:0230 _wait_ly_6
-00:0236 _wait_ly_7
-00:024c _print_results_halt_2
-00:024f mismatch_cb
-00:0257 _print_sl_data56
-00:0265 _print_sl_out56
-00:027f _print_sl_data57
-00:0289 _print_sl_out57
-00:029a _print_sl_data58
-00:02a4 _print_sl_out58
-00:02ad hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem
+00:0150 main
+00:01ce main@quit_inline_1
+00:01df mismatch
+00:01f5 mismatch@quit_inline_2
+00:0244 hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000008f _sizeof_main
+00000065 _sizeof_mismatch

M cinema/gb/mooneye-gb/misc/boot_regs-A/baseline_0000.png → cinema/gb/mooneye-gb/misc/boot_regs-A/baseline_0000.png

M cinema/gb/mooneye-gb/misc/boot_regs-A/manifest.yml → cinema/gb/mooneye-gb/misc/boot_regs-A/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: AGB}
+config:
+  gb.model: AGB

M cinema/gb/mooneye-gb/misc/boot_regs-A/test.gb → cinema/gb/mooneye-gb/misc/boot_regs-A/test.gb

M cinema/gb/mooneye-gb/misc/boot_regs-A/test.sym → cinema/gb/mooneye-gb/misc/boot_regs-A/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/boot_regs-A.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_regs-A.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

M cinema/gb/mooneye-gb/misc/boot_regs-cgb/baseline_0000.png → cinema/gb/mooneye-gb/misc/boot_regs-cgb/baseline_0000.png

M cinema/gb/mooneye-gb/misc/boot_regs-cgb/manifest.yml → cinema/gb/mooneye-gb/misc/boot_regs-cgb/manifest.yml

@@ -1,1 +1,2 @@
-config: {gb.model: CGB}
+config:
+  gb.model: CGB

M cinema/gb/mooneye-gb/misc/boot_regs-cgb/test.gb → cinema/gb/mooneye-gb/misc/boot_regs-cgb/test.gb

M cinema/gb/mooneye-gb/misc/boot_regs-cgb/test.sym → cinema/gb/mooneye-gb/misc/boot_regs-cgb/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/boot_regs-cgb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_regs-cgb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

D cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/baseline_0000.png

D cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/manifest.yml

@@ -1,1 +0,0 @@
-config: {gb.model: CGB}

M cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.gb → cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.gb

D cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.sym

@@ -1,216 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/gpu/vblank_stat_intr-C.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0169 fail_halt
-00:017d _wait_ly_4
-00:0183 _wait_ly_5
-00:0199 _print_results_halt_1
-00:019c _test_failure_cb_0
-00:01a4 _print_sl_data55
-00:01a9 _print_sl_out55
-00:01ac test_round1
-00:01b8 _wait_ly_6
-00:0203 finish_round1
-00:0221 test_round2
-00:022d _wait_ly_7
-00:0279 finish_round2
-00:029b test_round3
-00:02a7 _wait_ly_8
-00:02f1 finish_round3
-00:030f test_round4
-00:031b _wait_ly_9
-00:0366 finish_round4
-00:0368 test_finish
-00:c014 intr_vec_vblank
-00:c017 intr_vec_stat
-00:c01a round1
-00:c01b round2
-00:c01c round3

A cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.sym

@@ -0,0 +1,155 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/ppu/vblank_stat_intr-C.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0169 fail_halt
+00:0170 fail_halt@quit_inline_1
+00:017e test_round1
+00:018a test_round1@wait_ly_5
+00:01d5 finish_round1
+00:01f3 test_round2
+00:01ff test_round2@wait_ly_6
+00:024b finish_round2
+00:026d test_round3
+00:0279 test_round3@wait_ly_7
+00:02c3 finish_round3
+00:02e1 test_round4
+00:02ed test_round4@wait_ly_8
+00:0338 finish_round4
+00:033a test_finish
+00:ff91 intr_vec_vblank
+00:ff94 intr_vec_stat
+00:ff97 round1
+00:ff98 round2
+00:ff99 round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000003 _sizeof_intr_vec_vblank
+00000003 _sizeof_intr_vec_stat
+00000001 _sizeof_round1
+00000001 _sizeof_round2
+00000001 _sizeof_round3
+00000019 _sizeof_main
+00000015 _sizeof_fail_halt
+00000057 _sizeof_test_round1
+0000001e _sizeof_finish_round1
+00000058 _sizeof_test_round2
+00000022 _sizeof_finish_round2
+00000056 _sizeof_test_round3
+0000001e _sizeof_finish_round3
+00000057 _sizeof_test_round4
+00000002 _sizeof_finish_round4

M cinema/gb/mooneye-gb/update.py → cinema/gb/mooneye-gb/update.py

@@ -3,7 +3,7 @@ import os
 import os.path
 import shutil
 import yaml
-from cinema.util import dictMerge
+from cinema.util import dict_merge
 
 suffixes = {
     'C': 'CGB',
@@ -43,7 +43,7 @@ with open(os.path.join(dest, root, fname, 'manifest.yml'), 'r') as f:
                             manifest = yaml.safe_load(f) or {}
                     except IOError:
                         pass
-                    dictMerge(manifest, {
+                    dict_merge(manifest, {
                         'config': {
                             'gb.model': model
                         }

all repos — mgba @ 5018364c0140a0eb8ae8d3368651edd66784a4d9

mGBA Game Boy Advance Emulator