GB I/O: DMA register is R/W
Vicki Pfau vi@endrift.com
Thu, 28 Jun 2018 11:54:03 -0700
2 files changed,
3 insertions(+),
3 deletions(-)
M
CHANGES
→
CHANGES
@@ -39,6 +39,7 @@ - Qt: Improve FPS timer stability
- GBA Serialize: Fix loading channel 3 volume (fixes mgba.io/i/1107) - GBA SIO: Fix unconnected SIOCNT for multi mode (fixes mgba.io/i/1105) - GBA BIOS: Fix BitUnPack final byte + - GB I/O: DMA register is R/W Misc: - GBA Timer: Use global cycles for timers - GBA: Extend oddly-sized ROMs to full address space (fixes mgba.io/i/722)
M
src/gb/io.c
→
src/gb/io.c
@@ -190,6 +190,7 @@ }
GBIOWrite(gb, REG_SCY, 0x00); GBIOWrite(gb, REG_SCX, 0x00); GBIOWrite(gb, REG_LYC, 0x00); + GBIOWrite(gb, REG_DMA, 0xFF); GBIOWrite(gb, REG_BGP, 0xFC); if (gb->model < GB_MODEL_CGB) { GBIOWrite(gb, REG_OBP0, 0xFF);@@ -618,6 +619,7 @@ case REG_SCY:
case REG_SCX: case REG_LY: case REG_LYC: + case REG_DMA: case REG_BGP: case REG_OBP0: case REG_OBP1:@@ -642,9 +644,6 @@ case REG_OCPD:
case REG_SVBK: // Handled transparently by the registers goto success; - case REG_DMA: - mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address); - return 0; default: break; }